Design Engineer II

Cadence; Hyderabad; On-site; INR 1,000,000 - 1,800,000; Full time

Job summary

Cadence is seeking a talented ASIC design professional in Hyderabad to drive physical implementation flows, automate toolchains, and optimize PPA for complex IP cores across leading foundries. You will work with Genus, Innovus, and other Cadence tools to streamline the entire design flow and improve performance and power characteristics.

The ideal candidate has 2+ years in ASIC physical design, strong scripting skills (Python, Tcl), and proven leadership and collaboration abilities to deliver

Qualifications

• MS/MTech/BE/BTech in Electronics from reputed institutes with 2+ years' experience.
• Physical design experience in ASIC design environment.
• Knowledge of complete ASIC Design Flow including Synthesis, Physical Designing, Timing Analysis, Power Analysis and Formal Verification.
• Experience in Logic Synthesis and PPA optimization techniques, LEC debugging for production designs.
• Hands-on experience with synthesis flows and tools such as Genus, Fusion Compiler.
• Strong leadership, communication, analytical and problem-solving skills.
• Scripting with Python and Tcl.
• Self-motivated and good team player.

Responsibilities

• Development, automation and maintenance of EDA flows and scripts for physical implementation.
• Develop TFM to optimize PPA for IPs and Soft Controllers.
• PPA characterization and optimization of flows for performance- and power-oriented IP cores on advanced process nodes (TSMC, Intel, Samsung, Rapidus).
• Manage regression infrastructure tracking RTL/flow quality and PPA of key designs.
• Digital design implementation using Cadence EDA tools (Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus) and other backend tools.
• Develop automation scripts using AI tools to reduce design execution turnaround time.

Skills

Python scripting

Tcl scripting

Leadership

Communication

Analytical thinking

Problem solving

Education

MS/MTech/BE/BTech in Electronics

Tools

Genus

Innovus

Conformal

Litmus

Tempus

Voltus

Certus

Pegasus

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Development, automation and maintenance of EDA flows and scripts for physical implementation
• Develop TFM to optimize PPA for IP’s and Soft Controllers
• PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
• Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
• Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
• Develop automation scripts using AI tools and reduce design execution turnaround time
• Required skills –
• Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 2 + years' experience
• Physical design experience in ASIC design environment
• Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
• Prior experience in Logic Synthesis and PPA optimization techniques, Logic Equivalence Checks ( LEC ) debug experience for production designs
• A detailed understanding of synthesis flows, hands on experience in developing, debugging synthesis flows with EDA tools such as Genus, Fusion Compiler.
• Should have excellent leadership, communication, analytical and problem solving skills
• Solid scripting skills including Python and Tcl.
• Should be self-motivated and good team player.

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