Design Engineer II

Cadence; Bengaluru; On-site; INR 600,000 - 1,000,000; Full time

Job summary

Cadence in Bengaluru is looking for skilled engineers to lead post-silicon validation efforts in high-speed SERDES protocols. Candidates should have a solid background in Physical Layer electrical validation, hands-on lab experience, and ideally, some leadership exposure managing small teams. The role requires technical expertise in design and coding environments like Verilog and Python. This is an excellent opportunity for professionals eager to make an impact in technology.

Qualifications

• 2-4 years experience with BTech or 1-2 years with MTech in Physical Layer Electrical Validation.
• Experience with high-speed SERDES protocols like PCIe, USB, and ethernet.
• Hands-on experience using lab equipment like oscilloscopes and BERT.

Skills

High-speed SERDES protocol validation

Lab equipment usage (oscilloscopes, network analyzers)

FPGA design

Strong communication skills

Education

BE/BTech/ME/MTech or equivalent

Tools

Verilog

Python

C/C++

TCL

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Minimum Qualifications

• 2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post‑Silicon Physical Layer Electrical Validation
• Deep Physical Layer electrical validation experience on at least one high‑speed SERDES protocol such as PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO, etc.
• Strong hands‑on experience using lab equipment such as oscilloscopes, network analyzers, bit‑error rate testers (BERT), etc.
• BE/BTech/ME/MTech or equivalent.

Preferred Qualifications

• Experience managing small teams (at least 2 members and above)
• Experience leading the complete post‑silicon validation efforts for at least one full project
• 1-2 years of experience in FPGA design, PCB schematic and layout design & prototyping
• Pre‑silicon IP/SoC Physical Layer electrical validation experience related to board bring‑up & debugging
• Familiarity with Verilog RTL coding, FPGA coding, LabVIEW, Python, C/C++, TCL
• Experience conducting hiring interviews and mentoring new hires

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