Sr. Principal Product Engineer – Digital & Signoff Group (DSG)

Cadence; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

Cadence is seeking a Sr. Principal Product Engineer for the Digital & Signoff Group in Bangalore. In this role, you'll be the bridge between R&D and customers, influencing chip design software and solving complex design challenges at 7nm and below.

Ideal candidates will have significant experience in ASIC design, strong technical skills, and proficiency in scripting. This role offers a chance to work on impactful projects in a collaborative environment.

Qualifications

• 8+ years of industry experience with a Bachelor's; 6+ years with a Master's.
• Deep understanding of the full ASIC design flow.
• Proven hands-on experience with advanced nodes.

Responsibilities

• Serve as the primary P&R resource for development teams.
• Collaborate to track and resolve software issues.
• Execute competitive benchmarks to demonstrate Cadence’s edge.
• Develop customized RTL-to-GDSII methodologies.
• Partner with Product Marketing to align technical capabilities.

Skills

Place-and-route expertise

Timing closure

PPA optimization

Scripting in Tcl, Python, Perl

Communication skills

Education

Bachelors in Electronics Engineering (EE)

Masters in Electronics Engineering (EE)

Tools

EDA tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Sr. Principal Product Engineer – Digital & Signoff Group (DSG)

Location: Bangalore

Team: Cadence DSG (Digital & Signoff Group)

The Opportunity

Join Cadence’s Digital and Signoff Group (DSG) as a Product Engineer, where you will act as the vital bridge between R&D, Application Engineering, and our global customers. In this high-impact role, you will influence the next generation of chip design software, helping industry leaders solve complex physical design challenges at 7nm and below.

Key Responsibilities

• Technical Expert: Serve as the primary place-and-route (P&R) resource for internal development teams and external customers.
• Product Evolution: Collaborate with R&D to track, diagnose, and resolve software issues, ensuring a robust tool release cycle.
• Design Benchmarking: Execute competitive benchmarks to demonstrate Cadence’s edge in Power, Performance, and Area (PPA).
• Flow Innovation: Develop and deploy customized RTL-to-GDSII methodologies and scripts to meet specific customer design goals.
• Strategic Collaboration: Partner with Product Marketing to align technical capabilities with market needs and customer roadmaps.

Requirements

Education

• Bachelors in Electronics Engineering (EE) + 8 or more years of industry experience
• Masters in Electronics Engineering (EE) + 6 or more years of digital implementation experience

• Core Expertise: Deep understanding of the full ASIC design flow (RTL-to-GDSII) with a focus on physical design and timing analysis.
• Advanced Node Experience: Proven hands-on experience with timing closure and PPA optimization at 7nm, 5nm, or below.
• Tool Proficiency: High familiarity with industry-standard EDA tools for synthesis, placement, routing, and signoff.
• Scripting Skills: Proficiency in Tcl, Python, or Perl (familiarity with AI-driven productivity tools is a major plus).
• Communication: Strong verbal and written skills to translate complex technical issues into actionable solutions.

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