Lead Design Engineer

Cadence Design Systems; Hyderabad; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Cadence Design Systems is seeking a seasoned ASIC backend engineer in Hyderabad to drive physical design, automate flows, and optimize PPA across leading foundries. You will use Cadence tools to implement digital designs and contribute to full-chip floorplanning with AI-driven partitioning.

The role requires 5+ years in ASIC backend, strong scripting in Python and Tcl, and leadership and collaboration within a high-impact team.

Qualifications

• MS/MTech/BE/BTech in Electronics from reputed institutes.
• 5+ years of experience in physical design/ASIC backend.
• Excellent leadership, communication, analytical and problem-solving skills.

Responsibilities

• Develop, automate, and maintain EDA flows and scripts for physical implementation.
• Develop TFM to optimize PPA for IPs and soft controllers.
• PPA characterization and optimization of flow for performance-oriented and power-oriented IP cores across foundries (TSMC, Intel, Samsung, Rapidus).
• Manage regression infrastructure to monitor RTL/flow quality and PPA of key designs.
• Implement digital design using Cadence tools (Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus).
• Work on automation of full-chip floorplanning using AI-based partitioning.

Skills

Leadership

Communication

Analytical thinking

Problem solving

Full-chip floorplanning

Global clock distribution

Education

MS/MTech/BE/BTech in Electronics

Tools

Python

Tcl

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Development, automation and maintenance of EDA flows and scripts for physical implementation
• Develop TFM to optimize PPA for IP’s and Soft Controllers
• PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
• Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
• Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
• Candidate will be working on automation of Full chip floorplanning using latest AI tools. Involving in active AI agent based partition for Full Chip Floorplanning.
• Required skills –
• Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 5 + years’ experience
• Physical design experience in ASIC design environment
• Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
• Should have excellent leadership, communication, analytical and problem solving skills.
• Expertise on High frequency design methodologies for complete ASIC backend flows.
• Candidate with experience in Full Chip (SoC level) floorplanning, pin assignment, global clock distribution across all subsystems is a plus point.
• Good communication skills, strong analytical problem solving skills and willingness to learn quickly.
• Solid scripting skills including Python and Tcl.
• Should be self-motivated and good team player.

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