Senior Physical Design Engineer II

Cadence; Pune District; On-site; INR 900,000 - 1,600,000; Full time

Job summary

Cadence Pune is seeking a Senior Physical Design Engineer II to join our team. You will implement physical design of advanced Cadence IPs using Genus, Innovus, Tempus, and Voltus, and you will optimize PPA across 7nm, 5nm, 3nm, and 2nm nodes.

You will develop, automate, and maintain EDA flows and scripts for physical implementation, and you will help manage regression infrastructure to ensure RTL/flow quality and PPA for key designs, supporting benchmarking for customer engagements.

Qualifications

• Knowledge of complete ASIC Design Flow including synthesis, timing, power, and formal verification.
• Experience with Cadence digital design tools is a plus.
• Proficiency in Python, Perl, TCL, and Unix shell.
• Understanding of digital logic design and processor architecture.
• Excellent communication and problem-solving skills.
• Self-motivated and a good team player.

Responsibilities

• Implement physical design of advanced Cadence IPs using Cadence tools (Genus, Innovus, Tempus, Voltus).
• Characterize and optimize PPA for IP cores across 7nm, 5nm, 3nm, and 2nm nodes.
• Develop, automate, and maintain EDA flows and scripts for physical implementation.
• Manage regression infrastructure to track RTL/flow quality and PPA of key designs.
• Benchmark PPAs for customer engagements.

Skills

ASIC Design Flow

Cadence tools

Scripting (Python, TCL, Perl, Unix)

Digital logic design

Tools

Cadence Genus

Cadence Innovus

Cadence Tempus

Voltus

Job description

Cadence Pune is seeking a Senior Physical Design Engineer II to join our team.

About the Role

Experience: 2-5 years

Responsibilities

• Implement physical design of advanced Cadence IPs using Cadence EDA tools such as Genus, Innovus, Tempus, and Voltus.
• Characterize and optimize PPA for performance-oriented and power-oriented IP cores across advanced process nodes, including 7nm, 5nm, 3nm, and 2nm.
• Develop, automate, and maintain EDA flows and scripts for physical implementation.
• Manage regression infrastructure to track the quality of RTL/flow development and PPA of key designs.
• Participate in benchmarking PPAs for customer engagements.

Qualifications

• Knowledge of complete ASIC Design Flow, including Synthesis, Physical Design, Timing Analysis, Power Analysis, and Formal Verification.
• Experience with Cadence digital design tools is a plus.
• Proficiency in scripting languages such as Python, Perl, TCL, and Unix shell.
• Strong understanding of digital logic design, processor design, and computer architecture is desirable.
• Excellent communication, analytical, and problem-solving skills.
• Self-motivated and a good team player.

Required Skills

• Knowledge of complete ASIC Design Flow
• Experience with Cadence digital design tools
• Proficiency in scripting languages
• Strong understanding of digital logic design