Design Verification Engineer

HCLTech; Hyderabad, Chennai District, Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Benefits offered by this job

Competitive compensation

Learning and growth opportunities

Job summary

HCLTech seeks a Design Verification Engineer with 5-11 years of ASIC/SoC verification experience to build and run verification environments for complex digital designs.

You will work with SystemVerilog, UVM, and industry-standard simulators, delivering robust testbenches and achieving coverage goals in a collaborative engineering setting.

Qualifications

• 5–11 years of ASIC/SoC verification experience.
• Strong SystemVerilog and UVM proficiency.
• Expertise in functional verification for ASIC/SoC designs.
• Experience building and debugging verification testbenches.
• Solid understanding of digital design concepts and RTL verification.
• Hands-on with simulators such as VCS, Xcelium/Incisive, or Questa/ModelSim.
• Strong debugging and coverage closure/problem-solving skills.

Responsibilities

• Develop and execute verification environments for complex digital designs.
• Create and debug verification testbenches and checkers.
• Collaborate with design teams to validate RTL and ensure coverage goals.
• Analyze failures and drive debugging leading to functional closure.

Skills

SystemVerilog

UVM

ASIC/SoC verification

Testbenches

Digital design concepts

RTL verification

Debugging & coverage

Education

Bachelor's or Master's in ECE/EE/CS

Tools

VCS

Xcelium/Incisive

Questa/ModelSim

SVA

Python

Perl

Shell scripting

Job description

Design Verification Engineer | 5-10Years
We are looking for a Design Verification Engineer with 5-11 years of ASIC/SoC verification experience to develop and execute verification environments for complex digital designs.

Key Requirements:

• Strong experience in SystemVerilog and UVM
• Expertise in ASIC/SoC functional verification
• Experience building and debugging verification testbenches
• Good understanding of digital design concepts and RTL verification
• Hands-on experience with simulators such as VCS, Xcelium/Incisive, or Questa/ModelSim
• Strong debugging, coverage closure, and problem-solving skills

Good to Have:

• Experience with AXI/AHB/APB or other industry-standard protocols
• Knowledge of SVA, Python, Perl, or Shell scripting

Qualification:

• Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, or a related field

Why Join Us?

• Work on cutting-edge ASIC/SoC designs
• Collaborative engineering environment
• Excellent learning and growth opportunities
• Competitive compensation and benefits package