Senior Asic Verification Engineer

Vismay Talent; Hyderabad, Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Vismay Talent is seeking a Senior ASIC Verification Engineer for roles in Bengaluru/Hyderabad. The candidate will drive RTL front-end verification at IP, block or subsystem level, using SystemVerilog and UVM to verify PCIe/NVMe protocols and AXI/AHB interfaces.

The ideal candidate has 5+ years of relevant experience, strong debugging skills, and collaboration proficiency. This full-time on-site role requires hands-on verification and a proactive approach to problem solving.

Qualifications

• Minimum 5 years of RTL Front-end verification experience.
• Minimum 4 years SystemVerilog (SV) and UVM-based verification.
• Minimum 2 years of AXI/AHB interfaces.
• Minimum 2 years of PCIe and/or NVMe protocol verification.
• Strong debugging and problem-solving skills.
• Good communication and collaboration skills.
• Experience with ASIC simulation tools.

Responsibilities

• Develop and execute verification plans for IP, Block, and Subsystem RTL designs.
• Develop, maintain, and debug SystemVerilog/UVM-based verification environments.
• Create and execute test scenarios, test cases, and regression suites.
• Verify AXI/AHB interfaces and PCIe/NVMe protocols.
• Perform functional verification, debugging, failure analysis, and root-cause analysis.
• Analyze simulation results and identify RTL/design issues.
• Collaborate with RTL designers and other verification teams to resolve issues.
• Support regression execution and improve verification coverage.
• Apply advanced ASIC verification methodologies to ensure design quality.

Skills

SystemVerilog

UVM

PCIe/NVMe

AXI/AHB

Debugging

ASIC verification

Tools

Simulation tools

Job description

We have urgent opening for >>

Senior ASIC Verification Engineer [RTL / PCIe / NVMe] role,

JD:

Senior ASIC Verification Engineer RTL / PCIe / NVMe

Location: Bengaluru / Hyderabad
Experience: 5+ Years
Employment Type: Full-Time
Industry: Semiconductor / ASIC / VLSI
Requirement: Urgent

Role Overview

We are looking for an experienced ASIC Verification Engineer with strong hands‑on experience in RTL front‑end verification at IP, Block, or Subsystem level. The ideal candidate should have strong expertise in SystemVerilog, UVM, and protocol verification, with preferably strong PCIe verification experience.

Mandatory Skills & Experience

• Minimum 5 years of experience in IP, Block, or Subsystem-level RTL Front-end Verification.
• Minimum 4 years of hands‑on experience in SystemVerilog (SV) and UVM-based verification.
• Minimum 2 years of experience with AXI/AHB interfaces.
• Minimum 2 years of experience with PCIe and/or NVMe protocol verification.
• Strong debugging and problem‑solving skills.
• Good understanding of ASIC simulation tools and advanced verification methodologies.
• Good communication and collaboration skills.

Good to Have

• Strong hands‑on PCIe verification experience.
• Experience with NVMe verification.
• Scripting experience using Perl and/or Python.
• Experience working on complex ASIC/SoC verification environments.
• Knowledge of advanced verification techniques and methodologies.

Key Responsibilities

• Develop and execute verification plans for IP, Block, and Subsystem-level RTL designs.
• Develop, maintain, and debug SystemVerilog/UVM-based verification environments.
• Create and execute test scenarios, test cases, and regression suites.
• Verify AXI/AHB interfaces and PCIe/NVMe protocols.
• Perform functional verification, debugging, failure analysis, and root‑cause analysis.
• Analyze simulation results and identify RTL/design issues.
• Collaborate with RTL designers and other verification teams to resolve issues.
• Support regression execution and improve verification coverage.
• Apply advanced ASIC verification methodologies to ensure design quality.

Candidate Requirements

Only candidates with relevant and matching ASIC RTL Verification experience should be considered.

Candidates should demonstrate:

• Strong IP/Block/Subsystem verification experience.
• Strong SystemVerilog and UVM experience.
• Hands‑on AXI/AHB verification experience.
• Relevant PCIe/NVMe protocol verification experience.
• Good debugging and problem‑solving capabilities.
• Effective verbal and written communication.
• Experience with ASIC simulation and verification tools.

Important: Please avoid duplicate submissions. Candidates with strong PCIe verification experience will be preferred.