Design and Verification Engineer

Adhaan Solutions; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Adhaan Solutions in Bengaluru, India is seeking a verification engineer to develop and execute verification plans for digital/RTL designs. You will build and maintain SystemVerilog/UVM environments and testbenches, create test cases, and perform RTL simulation, debugging, and coverage analysis.

The role involves working with RTL design, architecture, and other engineering teams, contributing to methodology and regression improvements, and delivering timely verification across multiple projects.

Responsibilities

• Develop and execute verification plans for digital/RTL designs.
• Develop and maintain SystemVerilog/UVM-based verification environments and testbenches.
• Create and execute test cases to verify functional requirements and design specifications.
• Perform RTL simulation, debugging, and failure analysis.
• Develop functional and regression tests to ensure comprehensive design verification.
• Implement and analyze functional and code coverage to identify verification gaps.
• Develop and maintain SystemVerilog Assertions (SVA) where required.
• Debug design and verification issues and work closely with RTL Design, Architecture, and other engineering teams to resolve them.
• Participate in pre-silicon verification activities for ASIC/SoC designs.
• Analyze simulation results and track issues through closure.
• Contribute to verification methodology, automation, and regression improvements.
• Prepare verification reports and provide regular status updates on coverage, bugs, and verification progress.
• Support multiple projects and deliver verification activities within defined timelines.

Skills

SystemVerilog

UVM

RTL verification

Testbench development

Debugging

Coverage analysis

Tools

UVM environment

SystemVerilog Assertions

Job description

Roles & Responsibilities

• Develop and execute verification plans for digital/RTL designs.
• Develop and maintain SystemVerilog/UVM-based verification environments and testbenches.
• Create and execute test cases to verify functional requirements and design specifications.
• Perform RTL simulation, debugging, and failure analysis.
• Develop functional and regression tests to ensure comprehensive design verification.
• Implement and analyze functional and code coverage to identify verification gaps.
• Develop and maintain SystemVerilog Assertions (SVA) where required.
• Debug design and verification issues and work closely with RTL Design, Architecture, and other engineering teams to resolve them.
• Participate in pre-silicon verification activities for ASIC/SoC designs.
• Analyze simulation results and track issues through closure.
• Contribute to verification methodology, automation, and regression improvements.
• Prepare verification reports and provide regular status updates on coverage, bugs, and verification progress.
• Support multiple projects and deliver verification activities within defined timelines.

Immediate Joiners are preferred. Candidates available to join immediately or within a short notice period will be given priority.