Senior Engineer DV

Quest Global; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Quest Global in Bengaluru seeks a Verification Engineer to shape verification planning and develop robust test environments for IP, subsystem, or SoC levels. You will design test benches and vectors to simulate system behavior and ensure coverage-driven verification.

You will collaborate with design and system engineers, perform debugging, analyze results, and document processes. Experience with ModelSim/VCS and HDL-based verification is essential to deliver quality designs.

Qualifications

• Experience in verification planning and test development.
• Proficiency with HDL and verification methodologies.
• Familiarity with UVM and coverage-driven verification.
• Ability to document tests and results clearly.

Responsibilities

• Review design specifications and develop verification plans.
• Design and implement test benches and test vectors.
• Develop reusable verification environments at IP, subsystem, or SoC levels.
• Execute verification tests with simulation tools (ModelSim, VCS).
• Analyze test results, perform root cause analysis and propose fixes.
• Apply formal verification when applicable.
• Collaborate with design and system engineers; participate in design reviews.
• Document verification processes, plans, and results.

Job description

• Verification Planning and Test Development
• Review design specifications and requirements to develop comprehensive verification plans
• Design and implement test benches and test vectors to simulate system behavior
• Develop coverage-driven, reusable, and portable verification environments at IP, subsystem, or SoC levels
• Simulation and Debugging
• Execute verification tests using simulation tools such as ModelSim, VCS.
• Analyze test results, identify bugs, perform root cause analysis, and propose solutions
• Apply formal verification methodologies when applicable to ensure design correctness
• Collaboration and Communication
• Work closely with design engineers, architects, and system engineers to address design-related concerns
• Participate in design reviews and provide insights to improve system performance
• Document verification processes, test plans, and results for team reference and compliance.
• Tools and Methodologies
• Proficiency in hardware description languages (HDLs) such as Verilog, SystemVerilog, or VHDL
• Familiarity with scripting languages like Python, Perl, or TCL for automation
• Knowledge of Universal Verification Methodology (UVM) for building reusable test environments