CPU Floorplan Lead

Intel; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Intel in Bangalore seeks an experienced ASIC Physical Design Engineer to lead floorplanning and pin placement for CPU IP across SKUs. You will collaborate with Architecture, DFT and packaging teams to optimize chip planning, timing, and routability.

Strong tool expertise in ICC2 DP and Cadence Encounter is required. The role demands 10+ years in floorplanning, with a deep understanding of voltage/clock domains and ESD strategies, and a proven track record in die size estimation and physical

Qualifications

• 10+ years in floorplanning and ASIC integration.
• Experience with multiple voltage and clock domains and ESD strategies.
• Expertise with Floorplanning tools ICC2 DP and Cadence Encounter.
• Collaborate with Architecture, DFT and packaging teams to optimize chip planning.

Responsibilities

• Own floorplanning and pin placement for CPU IP across SKUs.
• Collaborate with Architecture, DFT and package teams for optimal chip planning.
• Evaluate floorplan tools, methods and flows; drive timing closure and routability.
• Support die size estimation and floorplan tool evaluation.

Skills

Floorplanning

Pin placement

Timing closure

Power distribution

SoC integration

VLSI design

Education

B.Tech / M.Tech in Electrical-Electronics Engineering

Masters in Electrical-Electronics Engineering with VLSI specialization

Tools

ICC2 DP

Cadence Encounter

Job description

Job Details

Defines the physical dimensions of the CPU IP with consideration for overall product costs such as die size optimization, die per reticle/good die per wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family. Performs integration of all dies in a package and completes the relevant checks before tapeout. Creates and physical database for the IP. Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspectratio. Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR. Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power.

Qualifications

Job Requirement: In this role you will be responsible for all the aspects of Floorplan and pin placement activities. You will engage with Architecture, DFT and package to arrive at optimal chip planning early in the design cycle. You will work closely with physical design cluster leads to comprehend design challenges and arrive at optimal floorplan. You will play critical role in die size estimation and in evaluating Floorplan tools, methods and flows. Planning boundaries and pin densities to facilitate high confidence timing closure and routability. With your broad understanding of physical design you will play a critical role in identifying and solving multitude design issues at partition/cluster and full chip. Expertise with multiple aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I-O planning and hard IP integration. Qualifications: Education: B.Tech. or M.Tech. in Electrical-Electronics Engineering with 10+ years' of experience. Preference: Master's Degree in Electrical-Electronics Engineering with VLSI-microelectronics specialization Minimum 4 years in floor planning. Expert user of Floorplanning tools such as ICC2 DP or Cadence Encounter. Key Skills: Experience with SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and advanced package technologies. Hierarchical design approach, top-down design, budgeting, timing and physical convergence. From a CAD tool perspective, experience with Floor planning tools, P and R flows, Physical Design Verification Flows is required. Familiar with various process related design issues including Design for Yield and Manufacturability.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Additional Locations

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.