Senior GPU Floorplan Design Engineer

NVIDIA Gruppe; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

NVIDIA Gruppe is seeking a GPU Floorplan design engineer in Bengaluru to design and implement advanced GPUs. This role combines architecture and physical design with a focus on feasibility studies and trade-offs, impacting both consumer graphics and AI technology.

The ideal candidate has a B.Tech/M.Tech and over 5 years of experience in ASIC physical design, with a solid understanding of timing and power distribution. Strong programming skills in languages like Python and C/C++ are essential.

Qualifications

• 5+ years of experience in floorplan, SOC planning, or ASIC physical design.
• Deep background in hardware engineering with focus on VLSI or Computer Architecture.
• Hands-on experience with chip-level or subsystem-level floorplanning.

Responsibilities

• Develop and optimize floorplans during early chip development.
• Drive area review process and identify improvement opportunities.
• Solve timing and routing congestion issues with design teams.

Skills

VLSI

ASIC physical design

Python

C/C++

Verilog

Education

B.Tech./M.Tech.

Tools

CAD tools

Job description

NVIDIA is seeking a talented GPU Floorplan design engineer to design and implement the world’s leading GPUs as part of a completely new team being built in Bangalore. This role sits at the intersection of architecture, RTL, performance analysis, and physical design, with a strong focus on path forward, early planning, feasibility studies, and physical trade‑off exploration. This position offers you a unique opportunity to craft and influence the design and development of the next generation GPU, allowing you to have real impact in a dynamic, technology‑focused company impacting product lines ranging from consumer graphics to self‑driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

What you will be doing:

• Working with architects, design leads, physical design leads and package leads to develop and craft and optimize floorplans during early chip development.
• Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
• Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
• Build tools and improve existing infrastructure to optimize chip area and speed of execution.

What we need to see:

• B.Tech./M.Tech. with 5+ years of experience in floorplan, SOC planning, ASIC Physical design or related roles.
• A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
• Hands‑on experience with chip‑level or subsystem‑level floorplanning and physical planning.
• Solid understanding of timing, congestion, power distribution, and physical constraints.
• Experience in Verilog, SystemVerilog or similar HVL.
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
• Strong communication and interpersonal skills and an ability & desire to work as a great teammate.
• Python, Perl and C/C++ programming language experience.

Ways to stand out from the crowd:

• Experience in driving development of large scale ASIC floorplan is a huge plus.