Physical Design Engineer ICE

Intel; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

Intel in India (Bangalore) seeks a Physical Design Engineer to design and verify chip layouts across cell, block, and full-chip designs. You will ensure accuracy and functionality, contributing to high-performance solutions that drive Intel's innovations.

The role involves cell/block-level layout creation, verification, and parasitic extraction, with hybrid work options in a fast-paced design environment.

Qualifications

• Bachelor's degree in Electronics, Electrical Engineering, or related field.
• Basic understanding of layout design and verification processes.
• Familiarity with ICC2 tools and TCL scripting.

Responsibilities

• Create and verify cell and block-level semi-custom layouts, including floor plans and schematic-to-layout verification.
• Conduct reliability verification, debug processes, and parasitic extraction to ensure design integrity.
• Utilize auto-place and route algorithms, custom polygon editing, and floor planning techniques for chip assembly.
• Execute full-chip assembly, packaging, and verification processes to meet project timelines and quality standards.
• Troubleshoot complex design issues and proactively implement solutions.
• Schedule, staff, and execute chip development projects, ensuring adherence to methodologies and flow developments.

Skills

TCL scripting

ICC2 tools

Layout design understanding

Education

Bachelor's degree in Electronics or Electrical Engineering

Tools

ICC2 tools

Job description

Job Details

Job Description:

Join our team as a Physical Design Engineer, where you'll contribute to creating advanced chip designs pivotal to Intel's innovation. In this role, you'll design and verify critical elements of chip layouts, ensuring accuracy and functionality across cell, block-level, and full-chip designs. Your work will have a direct impact on delivering high-performance solutions that drive Intel's technological advancements.

Business group

You will be part of Intel's technology development organization, focused on delivering cutting-edge chip designs that support Intel's broader mission of shaping the future of computing. This group is dedicated to enhancing design methodologies and tools, enabling efficiency and innovation in chip design and verification processes.

Key Responsibilities

• Create and verify cell and block-level semi-custom layouts, including floor plans, abstract view generation, and schematic-to-layout verification.


• Conduct reliability verification, debug processes, and parasitic extraction to ensure design integrity.


• Utilize auto-place and route algorithms, custom polygon editing, and floor planning techniques for chip assembly.


• Execute full-chip assembly, packaging, and verification processes to meet project timelines and quality standards.


• Troubleshoot complex design issues and proactively implement solutions.


• Schedule, staff, and execute chip development projects, ensuring adherence to methodologies and flow developments.

Qualifications

Minimum Qualifications

• Bachelor's degree in Electronics, Electrical Engineering, or a related field.


• Basic understanding of layout design and verification processes.


• Familiarity with ICC2 tools and methodologies.


• Demonstrated skills in TCL scripting, with practical application experience preferred.

Preferred Qualifications

• Strong problem-solving abilities and attention to detail in design verification.


• Effective communication and collaboration skills within cross-functional teams.


• Enthusiasm for staying updated on industry trends in physical design and chip development.

Job Type

Intel Contract Employee

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.