Senior Staff Engineer-SoC Floorplan Lead

EnCharge AI; Bengaluru; On-site; INR 6,500,000 - 9,000,000; Full time

Benefits offered by this job

Equity

Flat, bureaucracy-free culture

Startup environment

Job summary

EnCharge AI is seeking a hands-on SoC Floorplan Lead to own the physical foundation of its AI and Data Center SoCs. You will bridge architecture, logic design, and physical design, influencing micro-architecture for best-in-class PPA.

Lead critical AMS, SerDes, and PDN work on cutting-edge process nodes, collaborating with chip architects and RTL leads in a fast-paced startup environment.

Qualifications

• 12–20 years of hands-on physical design and floorplanning experience.
• Lead or primary owner of SoC-level floorplanning in data center/AI chip projects.
• Experience with bump planning, package constraints, and AMS integration.
• Strong collaboration with Architecture and RTL teams; drive PPA improvements.

Responsibilities

• Own the SoC floorplan from concept to tape-out for high‑performance AI/Data Center chips on advanced nodes (5nm/3nm).
• Partner with Architecture/RTL to provide physical feasibility and data‑flow planning.
• Lead bump planning, IO ring definition, and packaging constraints.
• Direct macro placement, pin assignments, and feedthroughs to optimize timing and routing.
• Develop scalable floorplanning workflows using Tcl/Python.

Skills

SoC Floorplanning

Physical Design

PPA Optimization

Leadership

Data Center / AI Chips

Scripting: Tcl / Python

Education

BS/MS/PhD in Electrical or Computer Engineering

Tools

Cadence Innovus

Job description

SoC Floorplan Lead - Principal Engineer / Senior Staff

www.EnchargeAi.com

The 10 Hottest Semiconductor Startups Of 2025 (So Far)

https://www.crn.com/news/components-peripherals/2025/the-10-hottest-semiconductor-startups-of-2025-so-far?page=11

The Role

We are seeking a highly skilled and hands‑on SoC Floorplan Lead to own the physical foundation of our next‑generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand‑in‑hand with Chip Architects and RTL Leads to influence micro‑architecture and ensure the physical implementation achieves best‑in‑class Power, Performance, and Area (PPA).

If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high‑energy start‑up environment, this is the role for you.

Key Responsibilities

• Top‑Level Floorplanning: Own the SoC‑level floorplan from concept to tape‑out for high‑performance, large‑scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below).
• Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data‑flow planning to achieve the absolute best PPA.
• Bump & Package Co‑Design: Lead bump planning and IO ring definition. Work with packaging teams on flip‑chip/advanced packaging constraints, ensuring optimal signal escape and power delivery.
• Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed‑Signal (AMS) IPs, high‑speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions.
• Power Delivery Network (PDN): Design and analyze the top‑level power grid, ensuring robust power delivery for high‑current AI workloads while minimizing IR drop.
• Pin Assignment & Feedthroughs: Manage macro placement, block‑level pin assignments, and top‑level feedthrough planning to optimize global timing and routing congestion.
• Methodology Development: Build and maintain scalable Floorplanning workflows and scripts (Tcl, Python) tailored for a lean, fast‑moving start‑up team.

Required Skills & Qualifications

• Experience: 12 -20 years years of hands‑on experience in Physical Design SoC Floor planning preferably in Datacenter domain, with at least 3 years acting as a lead or primary owner of SoC‑level Floorplanning.
• Domain Expertise: Proven track record of taping out large, complex chips—specifically for Data Center, Networking, or AI/Machine Learning applications.
• Start‑Up Mentality: Highly driven, self‑motivated, and comfortable with ambiguity. You take extreme ownership of your domain, pivot quickly when needed, and roll up your sleeves to get things done.
• Technical Depth:
• Deep understanding of how RTL structures and architectural decisions impact physical design PPA.
• Extensive experience with bump planning, flip‑chip package requirements, and die‑to‑package co‑optimization.
• Strong knowledge of analog/mixed‑signal IP integration, shielding, and custom routing constraints.
• Expertise with industry‑standard physical design tools ( Cadence Innovus).
• Education: BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

• Experience with multi‑die / chiplet integration (2.5D, 3D packaging, interposers, UCIe).
• Strong scripting and automation skills (Tcl, Python, Perl, Makefile).
• Knowledge of advanced clocking architectures (H‑trees, meshes) for highly synchronous AI fabrics.

What We Offer

• Impact: The opportunity to build ground‑up architecture and see your ideas taped out in cutting‑edge silicon.
• Equity: Competitive start‑up equity packages—when the company wins, you win.
• Culture: A flat, collaborative, and bureaucracy‑free environment surrounded by top‑tier industry veterans.