Physical Design Layout Engineer ICE

Intel; Bengaluru; Hybrid; INR 500,000 - 700,000; Part time

Job summary

Intel in Bengaluru is seeking a Physical Design Engineer on a contract basis. The role focuses on creating and optimizing chip layouts, conducting schematic-to-layout verifications, and improving floor plans to ensure design integrity.

The position expects 0–1 years of hands‑on experience or a fresh Master’s degree in Electronics or Electrical Engineering, with familiarity in ICC2 tools and TCL scripting considered a plus. The role supports a hybrid work model in India.

Qualifications

• Bachelor's degree in Electronics, Electrical Engineering, or a related field with 0–1 years hands-on experience in physical design or a Master's degree with no prior professional experience.
• Basic understanding of layout design and verification processes.
• Familiarity with ICC2 tools.
• Proficiency in TCL scripting is a plus.

Responsibilities

• Develop and refine physical chip designs including cell and block-level layouts and floor plans.
• Perform schematic-to-layout verification to ensure design integrity.
• Collaborate across teams to troubleshoot and deliver high-quality design solutions.
• Apply reliability verification and debugging to optimize chip performance.
• Contribute to project methodologies, flows, and verification processes.

Skills

Problem-solving

Team collaboration

Layout understanding

Education

Bachelor's in Electronics or Electrical Engineering

Master's in Electronics or Electrical Engineering (no prior experience)

Tools

ICC2 tools

TCL scripting

Job description

Job Details

Job Description: The Role and Impact As a Physical Design Engineer, you will focus on creating and optimizing chip designs at the physical level. You'll be responsible for crafting elements such as cell, block-level semi-custom layouts, FUB-level floor plans, and performing schematic-to-layout verification to ensure design integrity. Your contributions will directly impact the development and execution of complex chip methodologies, enabling Intel to deliver cutting‑edge technology to the marketplace.

Business group This role is part of Intel's broader semiconductor engineering organization, which is dedicated to designing, developing, and verifying innovative chip technologies. The team focuses on advancing physical design methodologies, ensuring reliability, and optimizing chip performance while supporting Intel's mission to create world‑class computing solutions.

Key Responsibilities

• Develop and refine physical chip designs, including cell and block‑level semi‑custom layouts, FUB‑level floor plans, abstract view generation, and schematic‑to‑layout verification.
• Conduct reliability verification, debug issues, and apply proactive intervention strategies to optimize chip performance.
• Utilize parasitic extraction, custom polygon editing, auto‑place and route algorithms, floor planning, and full‑chip assembly techniques to ensure design success.
• Collaborate across teams to troubleshoot complex design challenges and deliver high‑quality solutions.
• Participate in the execution of project methodologies, flow developments, and verification processes.

Qualifications

Minimum Qualifications

• Bachelor's degree in Electronics, Electrical Engineering, or a related field with 0 - 1 years of hands‑on experience in physical design, including skills gained through internships, academic projects, coursework, or hands‑on training OR a Master's degree in Electronics, Electrical Engineering, or a related field with no prior professional experience.
• Basic understanding of layout design and verification processes.
• Familiarity with ICC2 tools.
• Proficiency in TCL scripting is a plus.

Preferred Qualifications

• Strong problem‑solving skills and ability to troubleshoot complex design challenges effectively.
• Excellent collaboration and communication skills to work across diverse teams.
• Demonstrated interest in advancing semiconductor technologies and methodologies.

Job Type

Intel Contract Employee

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Additional Locations

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.