Backend Physical Design Engineer

Mployee.me; Bengaluru; On-site; INR 800,000 - 1,200,000; Full time

Job summary

Mployee.me seeks a seasoned EDA/Backend Engineer to drive silicon design through the full backend flow, from floorplanning to physical verification. You will lead timing constraints, ECOs, and STAs, leveraging Cadence/Synopsys/Mentor flows and automation to improve throughput.

The role requires strong scripting in Tcl/Perl, hands-on experience with 5nm or smaller nodes, and collaboration across multi-site teams.

Qualifications

• MSEE/MSCS with 6+ years backend design experience.
• Strong background in P&R flows, timing constraints, and physical constraints.

Responsibilities

• Understand SoC for top-down/bottom-up physical design integration in 5nm and below.
• Demonstrate deep knowledge of P&R flows and internal flows.
• Implement timing and functional ECOs and drive STA closure.
• Lead build automation flows and adapt existing ones for reuse.

Skills

Backend design

P&R flow expertise

Automation scripting

Education

MSEE

MSCS

Tools

Genus

Innovus

Quantus

Tempus

DC

Star-RCXT

PT

PrimeRail

Voltus

Redhawk

Job description

Job Description:

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.

Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities include, but not limited to:

• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality

Minimum Qualifications:

• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)
• A deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

R027663