Backend Physical Design Engineer

Broadcom; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Broadcom is seeking a Senior Engineer to lead backend physical design for advanced SoCs, ensuring Right-first-time silicon. The role emphasizes deep P&R expertise, timing closure, and automation in a collaborative, multi-site environment.

Responsibilities include top-down/bottom-up flow integration, floorplanning, partitioning, placement, clock tree, routing, and physical verification, with strong emphasis on tooling proficiency (Genus/Innovus/Quantus/Tempus) and scripting capabilities.

Qualifications

• MSEE or MSCS required with 6+ years of experience (BSEE/BSCS 8+ years).
• Deep understanding of backend digital design flow and SoC integration.
• Proficient with timing constraints and physical constraints.

Responsibilities

• Understand SoC top-down/bottom-up physical design integration in 5nm and below technologies.
• Work on P&R flows; adapt and catch up on internal flows.
• Implement timing and functional ECOs; work toward STA closure.
• Automation: build or adapt flows for reuse; improve TAT and quality.
• Lead by example and collaborate across multi-functional teams.

Skills

Backend design

Timing constraints

Cross-functional collaboration

Automation scripting

Education

MSEE/MSCS

BSEE/BSCS

Tools

Genus

Innovus

Quantus

Tempus

DC

Star-RCXT

PrimeRail/Voltus

Redhawk

Job description

Job Description: In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria

Job Description: In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities include, but not limited to:

• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synopsys/Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality

Minimum Qualifications:

• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)
• A deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

R027663