Backend Physical Design Engineer

Broadcom; Jigani; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Broadcom is seeking an experienced backend physical design engineer to lead layout activities for 5nm and below technologies. You will drive floorplanning, partitioning, placement, CTS, and routing, while ensuring tight timing and robust physical verification.

Candidates should master P&R flows, ECO implementation, and STA closure, and contribute automation to improve turn-around-time. Collaboration across sites and groups is essential.

Qualifications

• MSEE/MSCS with 6+ years (BSEE/BSCS 8+ years) preferred.
• Backend digital design flow understanding and timing constraints.
• Proficient with backend EDA tools across floorplan/partition/placement/cts/route.
• Proficiency in Tcl and Perl; strong analytical skills.
• Collaborates across multi-functional teams and time zones.
• Ability to lead automation or scripting efforts to improve throughput.

Responsibilities

• Lead and apply Broadcom design methodology for right-first-time silicon.
• Perform floorplanning, partitioning, placement, CTS, route; drive STA closure.
• Develop automation flows and adapt existing ones for reuse.
• Work with Cadence/Synopsys/Mentor tools for P&R, PV, and STA.
• Implement timing and functional ECOs; ensure design quality and milestones.

Skills

Floorplanning

Partitioning

Placement

CTS

Routing

Physical verification

P&R flows

ECO scripting

Tcl

Perl

Debugging

Collaboration across teams

Education

MSEE/MSCS

BSEE/BSCS

Tools

Genus/Innovus

Quantus/Tempus

DC/Star-RCXT/PT

PrimeRail/Voltus

Job description

Job Description

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.

Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities include, but not limited to:

• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality

Minimum Qualifications:

• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)
• A deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.