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Broadcom in Pune seeks a Lead Physical Design Engineer to drive SoC backend flows on 5nm and below. You will own P&R, timing closure, and physical verification, while mentoring engineers across different sites and time zones to deliver high-quality silicon.
The role requires 15+ years in physical design, deep EDA tool mastery (Cadence, Synopsys, Siemens) and scripting in Tcl/Perl to develop scalable automation. You will shape methodologies and improve turnaround times for complex projects.
As a Lead Physical Design Engineer, you will drive physical design implementation for complex SoC architectures on 5nm and advanced sub-5nm technology nodes. This role requires an exceptional balance of hands-on technical execution and strategic engineering leadership.You will own the development and implementation of P&R flows, physical verification, and timing closure, while actively driving methodology improvements and mentoring engineers across different sites and time zones to deliver high-quality silicon.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.