Backend Physical Design Engineer

4123 LSI India Research & Development Private Limited; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Equal opportunity employer

Job summary

Broadcom, Inc. seeks an experienced engineer to lead silicon design flow, focusing on right-first-time outcomes and advanced 5nm+ backend tasks. You will contribute to floorplanning, partitioning, placement, CTS, routing and verification, while advancing automation across the flow.

You will work with Cadence/Synopsys/Mentor tools for P&R, PV, and STA, and you will implement ECOs with Tcl/Perl-based automation, driving improvements in cycle time and quality across multi-functional teams.

Qualifications

• Deep understanding of backend digital design flow.
• Proficient in timing constraints and physical constraints.
• Experience with SoC P&R flows and industry EDA tools.

Responsibilities

• Understand SoC integration for 5nm and below technologies.
• Lead P&R, extraction, PV, and STA closure efforts.
• Implement timing and functional ECOs across flows.
• Build automation into existing flows and promote reuse.
• Lead by example with clear requisites and high TAT quality.

Skills

Backend digital design

Floorplanning

Partitioning

Placement

Clock tree synthesis

P&R flows

STA/Timing

ECOs

Automation scripting

Tcl/Perl

Education

MSEE / MSCS

BSEE / BSCS

Tools

Genus

Innovus

Quantus

Tempus

DC

Star-RCXT

PT

PrimeRail/Voltus

Job description

Job Description: In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities

• Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
• Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt.
• Implement timing and functional ECO
• P&R, Extraction, Physical verification, work towards STA closure
• Build automation flows wherever needed/adapt to existing flows for re-use
• Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO
• Needs to be automation savvy with high expertise in one of the programming languages used in the industry
• Clearly know requisites for executing his/her job and lead by example
• Bring tangible improvement in TAT with better quality

Minimum Qualifications

• MSEE/MSCS 6+ years (BSEE/BSCS 8+ years)
• A deep understanding of backend digital design flow
• Proficient in timing constraints, physical constraints
• Proficient in handling EDA tools across floorplan/partition/placement/cts/route stages for SoC TOP.
• Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk
• Proficiency in Tcl and Perl
• Excellent analytical skills
• Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

Broadcom is proud to be an equal opportunity employer.

We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.

We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series. Follow us on Linked In Broadcom Inc.