Associate III - VLSI DFT Engineer

UST; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

UST is seeking a skilled professional for a role focusing on hands-on experience in scan insertion, JTAG, ATPG, and coverage analysis. The ideal candidate should have proficiency in simulation debug with timing/SDF, along with the ability to debug and root cause simulation failures. Strong communication skills and a proactive attitude are essential. This position is based in Bengaluru, Karnataka, India.

Qualifications

• Hands-on experience in scan insertion, JTAG, ATPG, DRC, and coverage analysis.
• Proficiency in simulation debug with timing/SDF.
• Experience with LBIST and Mixed Signal Radar ICs is highly desirable.
• Ability to debug and root cause simulation failures.
• Must be proactive, collaborative, and detail-oriented.
• Strong interpersonal and communication skills (both oral and written).
• Self-motivated and flexible.

Skills

VLSI design

JTAG

Scan insertion

Simulation debug

Coverage analysis

Timing analysis

Job description

Role Description

• Hands‑on experience in scan insertion, JTAG, ATPG DRC, and coverage analysis
• Proficiency in simulation debug with timing/SDF
• Experience with LBIST and Mixed Signal Radar ICs is highly desirable
• Ability to debug and root cause simulation failures
• Must be proactive, collaborative, and detail‑oriented, capable of exercising independent judgment
• Strong interpersonal and communication skills (both oral and written)
• Self‑motivated and flexible

Skills

vlsi design, jtag, scan insertion, simulation debug, coverage analysis, timing analysis