Senior DFT Engineer/Lead

Tata Consultancy Services; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Tata Consultancy Services in Bengaluru is seeking a Senior DFT Engineer/Lead to architect and implement DFT strategies for advanced Custom SoC designs. You will collaborate with Design, Verification and Implementation teams to ensure DFT requirements are met.

Responsibilities include scan insertion, ATPG pattern generation, and memory and logic BIST. You will perform DFT simulations, analyze results for test coverage, debug DFT issues, mentor junior engineers, and identify opportunities to

Qualifications

• Well-versed in Verilog/VHDL RTL coding; hands-on DFT knowledge.
• Strong expertise in Post Silicon Readiness (Pattern Generation) and Silicon Debug.
• Mentor junior engineers and provide technical guidance; proactive and collaborative.

Responsibilities

• Architect and implement DFT strategies for advanced Custom SoC designs.
• Collaborate with Design, Verification and Implementation teams to meet DFT requirements.
• Perform scan insertion, ATPG pattern generation, and LBIST/ BIST implementation.
• Perform DFT simulations and analyze results to ensure test coverage and quality.
• Debug and resolve DFT-related issues throughout the design process.
• Mentor junior engineers and identify opportunities to optimize test time.

Skills

Verilog/VHDL RTL coding

Post Silicon Readiness

Silicon Debug

Mentoring & collaboration

Tools

Mentor DFT

Cadence tools

Synopsys EDA tools

ATPG/DFT analysis tools

Job description

Job Description

Role

Senior DFT Engineer/Lead

Required Technical Skill Set

Architect and implement DFT strategies for advanced Custom SoC designs. Collaborate with Design, Verification and Implementation teams to ensure DFT requirements are met. Perform scan insertion, ATPG pattern generation, and BIST (Memory and Logic) implementation. Perform DFT simulations and analyze results to ensure test coverage and quality. Debug and resolve DFT-related issues throughout the design process. Mentor junior engineers and provide technical guidance as needed. Identify Test time optimization opportunities.

Desired Experience Range

12-18 years

Location of Requirement

Bangalore

Desired Competencies (Technical/Behavioral Competency/Skills)

Must-Have

Well versed in Verilog/VHDL RTL coding, experienced in using Mentor DFT, Cadence and Synopsys EDA tools. Hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Must have worked on few SoC DFT effort at least, from start to end. Must be proactive, collaborative and detail-oriented capable of exercising independent judgment. Strong expertise in Post Silicon Readiness (Pattern Generation) and Silicon Debug.

Good to Have

Excellent understanding of logic design fundamentals and gate/transistor level implementation. Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions. Strong problem solving and debug skills across various levels of design hierarchies.