VLSI - DFT Architect

Capgemini; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Capgemini in Bengaluru seeks an experienced SoC Design-for-Test (DFT) Lead to drive DFT architecture, implementation, verification, and silicon bring-up for complex SoCs. The role requires deep expertise in scan compression, ATPG, JTAG/iJTAG, MBIST, and test integration methodologies.

You will lead cross-functional teams across Design, Verification, Physical Design, Product Engineering, and Manufacturing, develop automation flows with Python/Perl/TCL, and partner with EDA vendors to boost

Qualifications

• Experience leading DFT architecture and verification for complex SoCs.
• Strong expertise in scan compression, ATPG, JTAG/iJTAG, and MBIST.
• Ability to drive cross-functional teams across architecture to production test.

Responsibilities

• Lead DFT execution across multiple IPs and SoC programs.
• Mentor junior engineers and provide technical guidance on DFT best practices.
• Collaborate with Design, Verification, Physical Design, Product Engineering, and Manufacturing teams.
• Develop automation flows using Perl, Shell, TCL, or Python scripting.
• Collaborate with EDA vendors and internal methodology teams to improve productivity and test quality.
• Define and implement comprehensive DFT strategies for complex SoC designs.
• Architect and deploy Scan, ATPG, JTAG (IEEE 1149.x), IEEE 1500, IEEE 1687 (iJTAG), Scan Compression (EDT), MBIST, and advanced test infrastructures.
• Drive scan insertion and DFT implementation using Synopsys Fusion Compiler or equivalent industry-standard EDA tools.
• Develop and review DFT specifications, test architectures, and verification plans.
• Develop and validate STA constraints for various DFT modes.
• Investigate and root-cause silicon and tester failures, partnering with RTL, physical design, verification, and product engineering teams.
• Analyze compressed ATPG, MBIST, JTAG/IEEE1500, and iJTAG related failures.
• Support silicon bring-up, characterization, production ramp, and yield improvement activities.
• Drive test escape analysis and corrective action implementation.
• Excellent communication and stakeholder management skills.

Skills

DFT Leadership

ATPG

JTAG/iJTAG

MBIST

Scan Compression

Automation scripting

Tools

Synopsys Fusion Compiler

Perl

Shell

TCL

Python

Job description

Roles Responsibilities

We are seeking an experiencedSoC Design-for-Test (DFT) Leadto drive DFT architecture, implementation, verification, and silicon bring-up activities for complex SoCs. The ideal candidate will possess strong expertise in scan compression, ATPG, JTAG/iJTAG, MBIST, and test integration methodologies, while leading cross-functional teams through the complete DFT lifecycle from architecture definition to production test support.

Key Responsibilities

Technical Leadership

• Lead DFT execution across multiple IPs and SoC programs.
• Mentor junior engineers and provide technical guidance on DFT best practices.
• Collaborate effectively with Design, Verification, Physical Design, Product Engineering, and Manufacturing teams.
• Participate in design reviews, architecture discussions, and project planning activities.
• Develop automation flows using Perl, Shell, TCL, or Python scripting.
• Collaborate with EDA vendors and internal methodology teams to improve productivity and test quality.

DFT Architecture and Implementation

• Define and implement comprehensive DFT strategies for complex SoC designs.
• Architect and deploy Scan, ATPG, JTAG (IEEE 1149.x), IEEE 1500, IEEE 1687 (iJTAG), Scan Compression (EDT), MBIST, and advanced test infrastructures.
• Drive scan insertion and DFT implementation using Synopsys Fusion Compiler or equivalent industry-standard EDA tools.
• Develop and review DFT specifications, test architectures, and verification plans.
• Develop and validate STA constraints for various DFT modes.

ATPG and Test Development

• Generate high-quality ATPG patterns for stuck-at, transition, path delay, and bridge fault coverage.
• Perform ATPG coverage analysis, DRC closure, and optimization to achieve production test goals.
• Debug and resolve ATPG, scan chain, compression, and pattern-related issues.
• Validate ATPG patterns using simulation/debug environments.

Test Integration and Debug

• Investigate and root-cause silicon and tester failures, partnering closely with RTL, physical design, verification, and product engineering teams.
• Analyze compressed ATPG, MBIST, JTAG/IEEE1500, and iJTAG related failures.
• Support silicon bring-up, characterization, production ramp, and yield improvement activities.
• Drive test escape analysis and corrective action implementation.

Soft Skills

• Excellent communication and stakeholder management skills.
• Strong problem-solving and analytical abilities.
• Proven ability to lead technical teams and drive execution across geographically distributed teams.
• Ability to influence architecture and methodology decisions across organizations.