VLSI - DFT Architect

Capgemini Engineering; Bengaluru; On-site; INR 3,000,000 - 5,500,000; Full time

Job summary

Capgemini Engineering in Bengaluru seeks an experienced SoC DFT Lead to drive DFT architecture, implementation, verification, and silicon bring‑up for complex SoCs. You will lead cross‑functional teams through the complete DFT lifecycle, including scan compression, ATPG, JTAG/iJTAG, and MBIST.

The role requires strong leadership, collaboration with Design, Verification, Physical Design, and Manufacturing, and the ability to develop automation flows using Python, Perl, Shell, or TCL.

Qualifications

• Strong expertise in scan compression, ATPG, JTAG/iJTAG, MBIST, and test integration methodologies.
• Experience leading cross‑functional teams through the DFT lifecycle from architecture to production test support.
• Proficient in scripting languages (Python, Perl, Shell, TCL).

Responsibilities

• Lead DFT execution across multiple IPs and SoC programs.
• Mentor junior engineers and provide technical guidance on DFT best practices.
• Collaborate with Design, Verification, Physical Design, Product Engineering, and Manufacturing teams.
• Develop automation flows using Perl, Shell, TCL, or Python scripting.
• Collaborate with EDA vendors and internal methodology teams to improve productivity and test quality.
• Define and implement comprehensive DFT strategies for complex SoC designs.
• Architect and deploy Scan, ATPG, JTAG (IEEE 1149.x), IEEE 1500, IEEE 1687 (iJTAG), Scan Compression (EDT), MBIST, and advanced test infrastructures.
• Drive scan insertion and DFT implementation using Synopsys Fusion Compiler or equivalent industry‑standard EDA tools.
• Develop and review DFT specifications, test architectures, and verification plans.
• Develop and validate STA constraints for various DFT modes.
• Investigate and root‑cause silicon and tester failures, partnering with RTL, physical design, verification, and product engineering teams.
• Support silicon bring‑up, characterization, production ramp, and yield improvement activities.
• Drive test escape analysis and corrective action implementation.
• Excellent communication and stakeholder management skills.

Skills

DFT

ATPG

JTAG/iJTAG

MBIST

Scan compression

Test automation

Python

Perl

Shell

TCL

EDA tools

Fusion Compiler

Tools

Synopsys Fusion Compiler

ATPG tools

JTAG tools

iJTAG tools

Job description

Roles & Responsibilities

We are seeking an experienced SoC Design-for-Test (DFT) Lead to drive DFT architecture, implementation, verification, and silicon bring-up activities for complex SoCs. The ideal candidate will possess strong expertise in scan compression, ATPG, JTAG/iJTAG, MBIST, and test integration methodologies, while leading cross‑functional teams through the complete DFT lifecycle from architecture definition to production test support.

Technical Leadership

• Lead DFT execution across multiple IPs and SoC programs.
• Mentor junior engineers and provide technical guidance on DFT best practices.
• Collaborate effectively with Design, Verification, Physical Design, Product Engineering, and Manufacturing teams.
• Participate in design reviews, architecture discussions, and project planning activities.
• Develop automation flows using Perl, Shell, TCL, or Python scripting.
• Collaborate with EDA vendors and internal methodology teams to improve productivity and test quality.

DFT Architecture and Implementation

• Define and implement comprehensive DFT strategies for complex SoC designs.
• Architect and deploy Scan, ATPG, JTAG (IEEE 1149.x), IEEE 1500, IEEE 1687 (iJTAG), Scan Compression (EDT), MBIST, and advanced test infrastructures.
• Drive scan insertion and DFT implementation using Synopsys Fusion Compiler or equivalent industry‑standard EDA tools.
• Develop and review DFT specifications, test architectures, and verification plans.
• Develop and validate STA constraints for various DFT modes.

ATPG and Test Development

• Generate high-quality ATPG patterns for stuck‑at, transition, path delay, and bridge fault coverage.
• Perform ATPG coverage analysis, DRC closure, and optimization to achieve production test goals.
• Debug and resolve ATPG, scan chain, compression, and pattern‑related issues.
• Validate ATPG patterns using simulation/debug environments.

Test Integration and Debug

• Investigate and root‑cause silicon and tester failures, partnering closely with RTL, physical design, verification, and product engineering teams.
• Analyze compressed ATPG, MBIST, JTAG/IEEE1500, and iJTAG related failures.
• Support silicon bring‑up, characterization, production ramp, and yield improvement activities.
• Drive test escape analysis and corrective action implementation.

Soft Skills

• Excellent communication and stakeholder management skills.
• Strong problem‑solving and analytical abilities.
• Proven ability to lead technical teams and drive execution across geographically distributed teams.
• Ability to influence architecture and methodology decisions across organizations.