Associate III - VLSI

UST; Hyderabad; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

UST is seeking a hands-on verification engineer in Hyderabad to contribute to C/C++ and SystemVerilog testbench development. The role emphasizes coverage planning, closure, and verification of microprocessor-related blocks, including cache, coherency and power sequencing.

Candidates will gain exposure to clocking and reset strategies, power-up sequences and design-for-debug considerations, with an emphasis on VLSI verification techniques and industry-standard ISAs.

Qualifications

• Hands on verification experience with C/C++/SystemVerilog testbench development.
• Experience with coverage planning, coding and coverage closure.
• Experience with x86, ARM or any other industry standard microprocessor ISA.
• Experience with Cache, Coherency and Data-Consistency verification.
• Experience in clocking, reset, power-up sequences and power management verification.
• Knowledge of microprocessor design-for-debug (DFD) logic will be a plus.
• Understanding of low power design verification techniques is a plus.

Responsibilities

• Hands on verification & testbench development using C/C++ and SystemVerilog.
• Plan and implement coverage across verification plan and test suites.
• Analyze and debug microprocessor related verification issues.
• Verify cache, coherency, data-consistency, clocks, resets and power sequencing.

Skills

C++

SystemVerilog

Testing

RTL Design

VLSI

Physical Design

Business Analysis

Job description

Role Description

• Hands on verification experience with C/C++/SystemVerilog testbench development.
• Hands on experience with coverage planning, coding and coverage closure.
• Experience with x86, ARM or any other industry standard microprocessor ISA.
• Experience with Cache, Coherency and Data-Consistency verification.
• Experience in clocking, reset, power-up sequences and power management verification.
• Knowledge of microprocessor design-for-debug (DFD) logic will be a plus.
• Understanding of low power design verification techniques is a plus.

Skills

• Business Analysis
• C++
• Physical Design
• RTL Design
• SystemVerilog
• Testing
• VLSI