Sr Staff DFT Engineer (AI2542)

SiMa.ai; Bengaluru; In loco; INR 4.500.000 - 7.500.000; Tempo pieno

Descrizione del lavoro

SiMa.ai in Bengaluru, India, is seeking a Sr Staff DFT Engineer to lead block-level and SOC-level DFT architectures, SCAN, MBIST, JTAG, and test insertion flows. You will collaborate across cross-site teams, optimize coverage, and deliver pre- and post-silicon verification using VCS/Verdi and TCL/Perl automation.

The ideal candidate has 7+ years in VLSI DFT, Verilog HDL, strong debugging skills, and hands-on experience with Tetramax or Tessent, with excellent communication and self-driven

Competenze

• 7+ years of experience in VLSI DFT and related workflows.
• Strong Verilog HDL knowledge and design exposure.
• Experience with block- and SOC-level DFT in finFET technology.
• Proficient with Tetramax or Tessent.
• Ability to problem-solve and debug efficiently.
• Experience with simulators VCS/Verdi.
• Scripting with C/C++, TCL, Perl, Python.
• Able to work with cross-site teams.
• Excellent communication and self-driven team player.

Mansioni

• Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG
• Develop and execute test insertion flow for scan, MBIST, JTAG
• Estimate and achieve targeted test coverage.
• Run RTL and gate-level simulation for all DFT modes.
• Develop and debug timing constraints for all DFT modes.
• Verify test patterns pre-silicon and post-silicon
• Write scripts in TCL and Perl to achieve productivity enhancements through automation.

Conoscenze

DFT engineering

Verilog

VLSI design

Tetramax

Tessent

VCS

Verdi

Python

Perl

TCL

C/C++

Cross-functional teamwork

Communication skills

Formazione

BSEE/MSEE or equivalent

Strumenti

Synopsys Tetramax

Mentor Tessent

VCS

Verdi

Descrizione del lavoro

Sr Staff DFT Engineer

Job ID: AI2542

Job Location: Bangalore, India

This position requires a full-time, on-site presence in our Bangalore, India office.

Responsibilities

• Block-level and sub-system DFT micro-architecture including SCAN, MBIST, IP tests, JTAG
• Develop and execute test insertion flow for scan, MBIST, JTAG
• Estimate and achieve targeted test coverage.
• Run RTL and gate-level simulation for all DFT modes.
• Develop and debug timing constraints for all DFT modes.
• Verify test patterns pre-silicon and post-silicon
• Write scripts in TCL and Perl to achieve productivity enhancements through automation.

Required Background

• BSEE/MSEE or equivalent degree with 7+ years of experience.
• In-depth knowledge of VLSI design as well as hardware description languages such as Verilog.
• Experience with complex block-level and SOC-level DFT execution in advanced finFET technology.
• Deep knowledge with EDA tools such as Synopsys Tetramax or Mentor Tessent.
• Good problem solving and debug capabilities is a preferred plus.
• Good knowledge of hardware simulation tools like VCS, Verdi, etc.
• Proficient in scripting languages (C/C++/TCL/Perl/Python)
• Should be proficient at working with cross functional and cross site teams.
• Must possess good communication skills, be a self-driven individual and a good team player.

Personal Attributes

Can-do attitude. Strong team player. Curious, creative, and good at solving problems. Execution and results oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.