Associate III - VLSI DFT NOD

UST; Dadri; Presencial; INR 800 000 - 1 600 000; Tempo integral

Resumo da oferta

UST is seeking a VLSI Design Engineer in Dadri, India, requiring a strong understanding of Siemens Tessent tools for ATPG and MBIST.

The ideal candidate should have experience with various methodologies, including SSN and pattern generation, along with strong TCL and scripting skills. Responsibilities include coverage analysis, debugging simulation failures, and DFT checks. This role offers an opportunity to work on cutting-edge VLSI projects.

Qualificações

• Strong understanding of Siemens Tessent Tools for ATPG with SSN methodology.
• Experience with ICL, PDL, stuck-at and transition fault pattern generation.
• Good understanding of scan coverage and experience in carrying out coverage analysis.
• Experience in timing and gate-level simulations and debugging simulation failures.
• Experience in carrying out DFT DRC checks in RTL and analyzing the violations.
• Strong understanding of scan structures, IEEE 1149.1, IEEE 1687, ATPG methodology and flow.
• Good understanding of timing constraints, synthesis flow and scan insertion using DC/FC.
• Strong TCL/scripting knowledge.
• Strong understanding of Siemens Tessent tools for MBIST insertion and verification.
• Experience in MBIST insertion in RTL and pattern generation.
• Experience in ICL, PDL, IEEE 1149.1, IEEE 1687, MBIST verification and debugging simulation failures.
• Good understanding of MBIST algorithms, architecture, and diagnosis features.

Conhecimentos

VLSI design

Stuck-at fault

Siemens Tessent

ATPG

SSN methodology

ICL

PDL

Ferramentas

Siemens Tessent Tools

VCS

Descrição da oferta de emprego

Role Description

• Strong understanding of Siemens Tessent Tools for ATPG with SSN methodology
• Experience with ICL, PDL, stuck‑at and transition fault pattern generation
• Good understanding of scan coverage and experience in carrying out coverage analysis
• Experience in timing and gate‑level simulations and debugging simulation failures
• Experience in carrying out DFT DRC checks in RTL and analyzing the violations
• Strong understanding of scan structures, IEEE 1149.1, IEEE 1687, ATPG methodology and flow
• Good understanding of timing constraints, synthesis flow and scan insertion using DC/FC
• Strong TCL/scripting knowledge

MBIST

• Strong understanding of Siemens Tessent tools for MBIST insertion and verification
• Experience in MBIST insertion in RTL and pattern generation
• Experience in ICL, PDL, IEEE 1149.1, IEEE 1687, MBIST verification and debugging simulation failures
• Good understanding of MBIST algorithms, architecture, and diagnosis features
• Strong TCL/scripting knowledge

Verification

• Strong knowledge of ICL, PDL, IEEE 1149.1, IEEE 1687 and simulation tools such as VCS
• Experience in creation of DFT test bench structures, verifying DFX structures in RTL and debugging simulation failures
• Good understanding of DFT structures such as scan controller, OCC, EDT, JTAG, iJTAG, IOs, HSIO loopback and reset controller
• Strong TCL/scripting knowledge

Skills

• vlsi design
• stuck‑at fault
• siemens tessent
• atpg
• ssn methodology
• icl
• pdl