ASIC IP design engineer

Swediumglobal; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Benefits offered by this job

Job summary

Swedium Global is seeking an experienced ASIC IP Designer to take ownership of block- and subsystem-level designs for 5G/6G components. You will develop IP architectures, produce RTL in SystemVerilog, and sign off with timing and synthesis tools.

Key qualifications include 5+ years in ASIC IP Design, AXI/CHI AMBA, SpyGlass, Cadence/Synopsys suites, and scripting in TCL or Python. Collaboration with verification and architecture teams is essential.

Qualifications

• 5+ years of experience in ASIC IP Design.
• Understanding of ASIC technology, design environments, and methodologies.
• IP development from concept to micro-architecture.
• RTL creation and sign-off with SystemVerilog.
• RTL static sign-off tools such as SpyGlass.
• Understanding of Synthesis and Timing concepts.
• Scripting languages like TCL, Python, or similar.
• AMBA-based IP development using AXI and CHI. SystemVerilog Assertions.
• Experience with Cadence and Synopsys front-end and middle-end design suites.
• Understanding of radio access systems and low-power design with UPF.
• CI/CD environments (Jenkins), simulation/analysis (Simscope), and Jira.
• IP design for ARM-based embedded MCUs, wireless protocols, and DSP concepts.

Responsibilities

• Develop ASIC IP blocks and subsystems for 5G/6G tech.
• Take full ownership of a design at block or subsystem level.
• Generate comprehensive documentation throughout the design lifecycle.
• Perform digital design and RTL sign-off checks.
• Enhance and optimize design methodologies and processes.
• Collaborate with IP Architects to create detailed IP architecture and design specs.
• Work with verification engineers to review and refine verification plans.
• Build competence in the technical domain.
• Engage in cross-team collaboration to ensure successful project delivery.

Skills

ASIC IP design

SystemVerilog

RTl sign-off

AXI/CHI AMBA

TCL/Python scripting

Synthesis & timing concepts

IP architecture specification

Verification planning

CI/CD tools

Jenkins/Jira/Simscope

Tools

SpyGlass

Cadence

Synopsys front-end

Synopsys middle-end

Jenkins

Simscope

Jira

Job description

Swedium Global is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Experience - 5-10years

Role Summary

Examples of tasks (Exact need to be defined case by case)

• Develop ASIC IP blocks and subsystems, contributing to the advancement of 5G and 6G communication technology.

• Take full ownership of a design, at block or subsystem level. • Generate comprehensive documentation throughout the design lifecycle.

• Perform digital design and conduct all RTL sign-off checks.

• Continuously enhance and optimize design methodologies and processes.

• Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications.

• Work closely with verification engineers to review and refine verification plans.

• Build competence in the technical domain.

• Engage in cross-team collaboration to ensure successful project delivery.

Required skills

• 5+ years industry experience in ASIC IP Design.

• Strong Experience in/with:

- Understanding of ASIC technology, design environments, and methodologies.

- IP development from concept (High-level Spec) to Micro-architecture,

-RTL creation and sign-off with SystemVerilog

-RTL static sign-off tools such as SpyGlass

-Understanding of Synthesis and Timing concepts.

-Scripting languages like TCL, Python, or similar.

-AMBA-based IP development using AXI and CHI. SystemVerilog Assertions.

Additional Requirements:

• Experience with Cadence and Synopsys front-end and middle-end design suites.

Preferred Skills • Understanding of radio access systems and their components.

• Expertise in low-power design, including specifying power intent using UPF or similar standards.

• Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira).

• Experience in designing IPs for one or more of the following hardware domains:

- ARM-based embedded microcontroller systems including their control and interface peripherals (Ethernet, USB, CPRI).

-Wireless infrastructure specific protocols and interfaces and protocols.

- Implementation of hardware-based digital signal processing systems (filters, adaptation, knowledge of CFR, DPD, Digital up-conversion and down-conversion chains etc)