ASIC Backend engineer

Swediumglobal; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Swedium Global is hiring an ASIC Backend Engineer in India to work on an omiste project in Bangalore with hybrid onsite aspects. You will contribute to backend tasks such as synthesis, timing analysis, and power optimization, using Synopsys tools and scripting to automate workflows.

The role requires 5+ years in backend development for ASICs, familiarity with EDA tools, and collaboration across cross-functional teams.

Qualifications

• 5+ years in backend development for ASIC/semiconductor projects.

Responsibilities

• Assist in backend tasks: synthesis, constraints setup, equivalence checks, placement & routing.
• Support STA sign-off and optimize timing/area/power with Synopsys tools.
• Develop scripts (Python/TCL/Linux) to automate workflows and improve efficiency.
• Contribute to low-power design using UPF and assist in physical implementation discussions.

Skills

Backend development

Synthesis

Static timing analysis

Power optimization

Scripting (Python/TCL/Linux shell)

Tools

Synopsys Design Compiler

Fusion Compiler

PrimeTime

ICC2/ Innovus

Formality/LEC

Git

Spyglass

Job description

Swedium Global is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Location: Onsite in Bangalore or Chennai (Hybrid)

We are looking for a skilled ASIC Backend Engineer for an omiste project in Bangalore

Role:
• Assist in backend development tasks, including synthesis, constraints setup,
equivalence checking, and place-and-route under guidance, contributing to
the delivery of high-quality digital ASICs.
• Support the static timing analysis, timing sign-off activities, and help with
optimizing timing/area/power using Synopsys tools (Design Compiler,
PrimeTime, ICC2/FC/Innovus) with mentorship.
• Gain hands-on experience with EDA tools and help develop scripts (Python,
TCL, Linux Shell) to automate processes and improve project efficiency.
• Contribute to innovations in low-power design using UPF and assist in
providing input on physical implementation and floor planning.
• Work collaboratively with cross-functional teams in a supportive, knowledgesharing
environment, ensuring smooth integration and execution.

Required skills
• 5+ Years of experience in backend development, with growing specialization
in synthesis, static timing analysis (STA), and power optimization within
semiconductor design.
• Contributed to multiple successful ASIC tape-outs, gaining hands-on
exposure to the full development cycle.
• Hands-on Knowledge and proficiency in EDA tools (Synopsys Design
Compiler, Fusion Compiler, PrimeTime, ICC2/Innovus, Formality/LEC) for
timing, area, power closure on advanced technology nodes.
• Good to have experience in scripting languages (Python, Perl, TCL, and Linux
Shell) to automate and streamline workflows.
• Comfortable in UNIX/Linux environments, essential for efficient and effective
backend operations.
• Commitment to Quality is a keen eye for detail and experience maintaining
high standards in complex, high-impact projects
• Knowledge on low-power design techniques, including UPF application and
VHDL/System Verilog for RTL2GDS flows.

Preferred Skills
• Good to have knowledge on Multi/Many-Core CPU architectures.
• Proficient in Git, and Synopsys tools like Spyglass, Design Compiler, and
Formality for optimized backend development.
• Familiarity with mobile communication standards, telecom, floor planning,
and physical implementation to enhance ASIC design effectiveness.