Analog Design Engineer

Swediumglobal; Bengaluru; On-site; INR 800,000 - 1,500,000; Full time

Job summary

A growing System Engineering and Solution Company in Bengaluru is seeking an experienced Analog Design Engineer to design, simulate, and verify high-performance analog blocks. The ideal candidate will have a Bachelor's/Master's in Electrical/Electronics Engineering and 3-5 years experience in analog transistor-level design in CMOS. Proficiency in EDA tools like Cadence Virtuoso is essential. This role involves collaboration with layout engineers and performance optimization to ensure successful designs across advanced technology nodes.

Qualifications

• 3-5 years of hands-on experience in analog transistor-level design (CMOS).
• Deep understanding of semiconductor device physics.
• Experience with deep sub-micron technology nodes (e.g., 28nm).

Responsibilities

• Design and simulate analog IP blocks such as Operational Amplifiers.
• Take ownership of block-level design from initial specs to GDSII release.
• Collaborate with layout engineers on layout optimization.

Skills

Analog circuit principles

EDA tools (Cadence Virtuoso)

Problem-solving skills

Scripting languages (Tcl, Python, Skill)

Education

Bachelor's/Master's degree in Electrical/Electronics Engineering

Tools

Cadence Virtuoso

Spectre

Calibre DRC/LVS/PEX

Job description

Swedium Global is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

About the Role

We are seeking a highly motivated and skilled Analog Design Engineer to join our growing Analog/Mixed-Signal design team. You will be responsible for the design, simulation, and verification of high-performance analog blocks in advanced technology nodes. As a key member of the team, you will contribute to defining specifications, circuit design, and supervising layout to ensure first-pass silicon success.

Key Responsibilities

Circuit Design & Simulation: Design and simulate analog IP blocks such as Operational Amplifiers, Comparators, Bandgap References, LDOs, PLLs, DLLs, Oscillators, or Data Converters (ADC/DAC).

Block-Level Ownership: Take ownership of block-level design from initial specs to GDSII release.

Performance Optimization: Perform detailed transistor-level simulations considering PVT (Process, Voltage, Temperature) variations, mismatch, and noise analysis.

Layout Supervision: Collaborate closely with layout engineers on top-level floorplanning and layout optimization, ensuring adherence to design rules (DRC) and layout-versus-schematic (LVS).

Post-Silicon Support: Assist in post-silicon validation, debugging, and characterization.

Documentation: Prepare comprehensive design review documents, circuit simulations, and layout notes.

Required Qualifications

Education: Bachelor's/Master's degree in Electrical/Electronics Engineering.

Experience: 3-5 years of hands-on experience in analog transistor-level design (CMOS).

Technical Skills:

Deep understanding of analog circuit principles and semiconductor device physics.

Proficiency in EDA tools: Cadence Virtuoso (Schematic, Layout), Spectre/SpectreAPS/SpectreX, or HSPICE.

Experience with deep sub-micron technology nodes (e.g., 28nm, 16nm, 7nm, or FinFET).

Familiarity with Physical Verification Tools: Calibre DRC/LVS/PEX.

Soft Skills: Strong problem-solving skills, ability to work independently, and excellent communication skills.

Preferred Skills

Experience with scripting languages (Tcl, Python, or Skill) for automation.

Knowledge of AMS (Analog Mixed-Signal) simulation and behavioral modeling (Verilog-A).

Experience in Power Management (PMIC) or High-Speed SerDes.