Analog layout Engineer

Best NanoTech; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

A leading technology firm in Bengaluru is looking for a highly experienced Senior Analog Layout Engineer. You will lead the design of complex analog mixed-signal blocks and collaborate closely with circuit designers to optimize layouts for performance. The ideal candidate has over 7 years of experience and a proven track record in FinFET technologies. This full-time position offers the opportunity to mentor junior engineers and improve design flow efficiency.

Qualifications

• 7+ years of hands-on analog layout experience.
• Expert proficiency with Cadence Virtuoso XL/GXL and Mentor Calibre.
• Proven track record of successful tape-outs in FinFET technologies.

Responsibilities

• Lead the physical design of complex analog mixed-signal blocks.
• Collaborate closely with circuit designers for layout optimization.
• Drive the physical verification process using Calibre.

Skills

Analog layout experience

Cadence Virtuoso XL/GXL

Mentoring junior engineers

Knowledge of floorplanning

Understanding of signal integrity

Tools

Mentor Calibre

Job description

At Best Nanotech, we are pushing the boundaries of high-performance analog/mixed‑signal design. We are currently seeking a highly experienced Senior Analog Layout Engineer to join our growing team in Bengaluru.

This is a senior‑level role requiring deep technical expertise in advanced process nodes and the ability to lead complex layout activities from initial floorplanning to final tape‑out.

Key Responsibilities

• Lead the physical design of complex analog mixed‑signal blocks (e.g., SerDes, PLL, ADC/DAC, PMIC, High‑speed I/O) in advanced FinFET nodes (7nm/5nm/3nm).
• Collaborate closely with circuit designers to optimize layout for performance, focusing on matching, parasitics, EM/IR drop, and signal integrity.
• Own top‑level floorplanning, block integration, and power grid redistribution layers (RDL).
• Drive the physical verification process (DRC, LVS, ERC, ANT) using Calibre and resolve complex violations.
• Mentor junior layout engineers, define layout methodologies, and improve design flow efficiency.

Required Skills & Experience

• 7+ years of hands‑on analog layout experience.
• Expert proficiency with Cadence Virtuoso XL/GXL and Mentor Calibre.
• Proven track record of successful tape‑outs in FinFET technologies.
• Deep understanding of analog layout concepts: common‑centroid matching, shielding, guard‑ringing, and latch‑up prevention.
• Experience with top‑level integration and floorplanning challenges.

Seniority Level

Mid‑Senior level

Employment Type

Full‑time

Job Function

Engineering and Information Technology

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