Senior Analog Layout Engineer | 4+ Years

leadIC Design Pvt Ltd; Hyderabad; Hybrid; INR 900,000 - 1,400,000; Full time

Job summary

LeadIC Design Pvt Ltd is seeking an experienced Analog Layout Engineer to join its hybrid team across Bengaluru, Pune, or Hyderabad. The role demands deep expertise in full-custom analog and mixed-signal IC layout and hands-on work with advanced nodes.

You will implement layouts with Cadence Virtuoso, ensure device matching and parasitic optimization, perform DRC/LVS/PEX checks, and collaborate with circuit designers to tape-out reliable ICs.

Qualifications

• 4-10 years of relevant Analog Layout Engineering experience.
• Hands-on experience with TSMC 2nm / 3nm / 5nm / 7nm process nodes.
• Cadence Virtuoso proficiency.
• Full-custom analog and mixed-signal IC layout.
• DRC, LVS, ERC, and PEX experience.
• Device matching and parasitic optimization.
• Tape-out support experience.
• Availability to join immediately or within 30 days.
• Experience with advanced-node analog or mixed-signal designs.
• Understanding of layout-dependent effects and matching-sensitive circuits.
• Collaboration with analog design and verification teams.

Responsibilities

• Design and implement full-custom analog and mixed-signal IC layouts using Cadence Virtuoso.
• Develop precision layouts for analog circuits, ensuring device matching, symmetry, and optimal floorplanning.
• Apply common-centroid, interdigitation, shielding, and other layout techniques to minimize mismatch and parasitic effects.
• Perform and debug DRC, LVS, ERC, and PEX checks to achieve layout sign-off readiness.
• Optimize parasitic resistance and capacitance while meeting performance, area, and reliability requirements.
• Collaborate with circuit designers and verification teams to resolve layout-related issues.
• Support physical verification, design iterations, and tape-out activities.
• Follow process design rules and technology-specific layout guidelines for advanced semiconductor nodes.

Skills

Analog Layout

Cadence Virtuoso

TSMC Nodes

Device Matching

Common-Centroid

Parasitic Optimization

DRC/LVS/PEX

Tape-out Support

Layout Debugging

Floorplanning

Tools

Cadence Virtuoso

Job description

• Analog Layout Engineer | 4-10 YearsCompany: LeadIC Design Pvt LtdEmployment Type: Full-timeWorkplace Type: HybridLocation: Bengaluru,Pune, HyderabadExperience: 4-8 yearsNotice Period: Immediate to 30 days onlyAbout the RoleLeadIC Design is looking for experienced Analog Layout Engineers with strong expertise in full-custom analog and mixed-signal IC layout, particularly at advanced technology nodes.The ideal candidate will have hands-on experience with TSMC 2nm, 3nm, 5nm, or 7nm technologies and solid understanding of device matching, parasitic optimization, physical verification, and tape-out requirements.Key ResponsibilitiesDesign and implement full-custom analog and mixed-signal IC layouts using Cadence Virtuoso.

• Design and implement full-custom analog and mixed-signal IC layouts using Cadence Virtuoso.

• Develop precision layouts for analog circuits, ensuring device matching, symmetry, and optimal floorplanning.

• Apply common-centroid, interdigitation, shielding, and other layout techniques to minimize mismatch and parasitic effects.

• Perform and debug DRC, LVS, ERC, and PEX checks to achieve layout sign-off readiness.

• Optimize parasitic resistance and capacitance while meeting performance, area, and reliability requirements.

• Collaborate with circuit designers and verification teams to resolve layout-related issues.

• Support physical verification, design iterations, and tape-out activities.

• Follow process design rules and technology-specific layout guidelines for advanced semiconductor nodes.

• Required QualificationsExperience: 4-10 years of relevant Analog Layout Engineering experience.

• Technology: Hands-on experience with TSMC 2nm / 3nm / 5nm / 7nm process nodes.

• EDA Tool: Strong proficiency in Cadence Virtuoso.

• Layout Expertise: Full-custom analog and mixed-signal IC layout.

• Physical Verification: Practical experience with DRC, LVS, ERC, and PEX.

• Core Skills: Device matching, common-centroid layout, shielding, parasitic optimization, and layout debugging.

• Tape-out: Experience supporting layout sign-off and tape-out activities.

• Availability: Must be available to join immediately or within 30 days.

• Preferred SkillsExperience working with advanced-node analog or mixed-signal designs.

• Understanding of layout-dependent effects, parasitic extraction, and matching-sensitive circuits.

• Experience collaborating with analog design and physical verification teams.