Analog Layout Engineer

Incise Infotech Pvt. Ltd.; Bengaluru; On-site; Full time

Job description

Analog & Mixed Signal Layout Design Full Custom IC Layout Floorplanning & Routing Device Matching Techniques Common Centroid Layout Parasitic Extraction DRC LVS ERC Verification EM/IR Analysis Guard Ring & Shielding Techniques ESD Protection Concepts Cadence Virtuoso Calibre Assura/PVS CMOS Technology PLL Layout ADC/DAC Layout LDO Layout Bandgap Layout Tape-out Support

Job Description

About the Role

We are looking for a skilled and detail-oriented Analog Layout Engineer to join our VLSI design team in Bangalore. The ideal candidate will have strong expertise in custom analog/mixed-signal layout design and a deep understanding of semiconductor manufacturing processes. You will work closely with circuit designers to develop high-performance, area-efficient, and manufacturable layouts for advanced technology nodes.

Key Responsibilities

• Develop and implement full-custom analog and mixed-signal layouts for blocks such as:
• PLLs
• ADC/DAC
• LDOs
• Bandgap references
• Charge pumps
• SRAM/compiler-related analog blocks
• Perform floorplanning, device matching, routing, shielding, and parasitic-aware layout techniques.
• Ensure layouts meet DRC, LVS, ERC, and EM/IR requirements.
• Work closely with circuit design and verification teams for layout optimization and silicon debug.
• Handle extraction and post-layout simulation support.
• Follow best practices for reliability, matching, and noise-sensitive designs.
• Support tape-out activities and coordinate with foundry requirements.
• Contribute to layout methodology improvements and automation initiatives.

Required Skills & Qualifications

• Bachelor’s or Master’s degree in Electronics/ECE/VLSI or related field.
• 3–8 years of hands‑on experience in analog/custom layout design.
• Strong understanding of analog layout concepts, matching techniques, common centroid layout, guard rings, shielding, latch‑up prevention, ESD and reliability rules.
• Experience with advanced process nodes (180 nm to 5 nm preferred).
• Proficiency in layout tools such as Cadence Virtuoso, Calibre, Assura/PVS.
• Good understanding of DRC/LVS/ERC and parasitic extraction flows.
• Knowledge of FinFET technology is an added advantage.
• Ability to work independently and collaborate across cross‑functional teams.

Preferred Skills

• Experience with high‑speed or low‑power analog designs.
• Exposure to mixed‑signal SoC environments.
• Scripting knowledge in SKILL/Python/TCL is a plus.
• Prior experience in complete chip tape‑outs.

What We Offer

• Opportunity to work on cutting‑edge semiconductor technologies.
• Collaborative and innovation‑driven work environment.
• Career growth opportunities with leading VLSI programs.
• Competitive compensation and benefits.

Interested can contact at [e-mail]