Analog Layout Engineer

UST; Hyderabad; On-site; INR 2,800,000 - 5,000,000; Full time

Job summary

UST in Hyderabad is seeking an experienced Analog Mixed-Signal Layout Engineer to work on high-speed blocks at advanced nodes. You will design and optimize layouts, rings, dividers, and bias cells in 2nm/3nm processes, ensuring tight verification and sign-off.

You will debug layout issues across flows, own tasks with minimal supervision, and document design views. 6–9 years in Cadence tools and scripting will be essential for success.

Qualifications

• 6–9 years hands-on experience in block/module layouts.
• Proficient with Cadence layout tools and verification flows.
• Knowledge of scripting in Shell, Perl, SKILL; Excel helpful.

Responsibilities

• Create custom layouts for analog/digital blocks (ring oscillators, dividers, bias cells) in advanced nodes.
• Debug and fix layout issues across verification flows.
• Take on varied tasks with minimal supervision and ownership.
• Ensure completed layouts meet quality and sign-off criteria.
• Prepare design views and documentation as required.

Skills

Scripting (Shell, Perl, SKILL)

Layout design

Education

B.Tech/B.E./MS/M.E./MTech in Electrical Engineering

Tools

Cadence Layout design tools

Cadence Virtuoso EXL/GXL

Calibre

Job description

Looking for only IMMEDIATE to 1Month Joiners.

Analog Mixed Signal Layout Engineer:

Responsibilities will include but not limited to following:

• Custom layouts for High-Speed Custom Analog/Digital blocks, such as Ring Oscillators, Dividers, Bias Blocks (Voltage & Current references), pre-drivers etc. in TSMC 2nm & 3nm,
• Independent in debugging and resolving the layout fixes in various verification flows
• Flexible to take different tasks in project.
• Execute tasks with minimum supervision/tracking
• Have accountability and ownership on blocks & tasks assigned.
• Completed layout designs, with desired quality, with all specified verification flows clean
• Create and check all relevant design views using sign-off tools.
• Documentation as per requirement.

Desired Qualification:

• B.Tech/B.E./MS /M.E. /M tech in Electrical Engineering
• 6-9 Years of hands-on experience in block/module layouts with Cadence Layout design tools, exp in TSMC 5nm or lower node is must
• Well versed with layout design and verification tools - Cadence Virtuoso EXL/GXL, Calibre etc.
• Knowledge of scripting (SHELL, PERL, SKILL), excel is good to have.