Analog layout Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd is seeking an experienced Analog Layout Engineer with 4+ years of hands-on expertise in custom layout development for lower-node and advanced semiconductor technologies. The role focuses on translating circuit designs into optimized layouts, ensuring robustness and compliance with physical verification processes.

You will collaborate closely with Analog Design, Circuit Design, and Technology teams to deliver high-quality layouts, manage DRC/LVS/ERC activities, and

Qualifications

• 4+ years of relevant experience in analog / custom layout design.
• Strong hands-on experience with analog layout and physical design.
• Experience on lower-node / advanced semiconductor technologies.
• Strong knowledge of DRC, LVS, ERC and physical verification.
• Good understanding of analog layout concepts and matching techniques.
• Experience with Cadence Virtuoso or equivalent custom layout tools.
• Good understanding of CMOS devices, parasitics and layout-dependent effects.
• Experience in handling complex analog blocks and resolving layout issues.
• Ability to work independently as well as with cross-functional teams.

Responsibilities

• Develop custom analog and mixed-signal layouts for various IPs and blocks.
• Work on lower-node technologies and advanced process nodes (FinFET or similar).
• Translate schematics and design requirements into optimized physical layouts.
• Perform layout implementation, optimization, and physical verification.
• Handle DRC, LVS, ERC and other verification activities and resolve violations.
• Collaborate with Analog Design, Circuit Design, Physical Verification and Technology teams.
• Analyze and resolve layout-related design issues and improve layout performance.
• Optimize layouts for area, matching, parasitics and performance.
• Perform post-layout verification and debugging.
• Ensure layouts meet foundry rules and technology requirements.
• Support design reviews, tape-out activities and project milestones.
• Maintain documentation and follow established layout methodologies.

Skills

Analog layout design

Analog layout and physical design

Lower-node / advanced process tech

DRC, LVS, ERC & physical verification

Analog layout concepts & matching

Cadence Virtuoso

CMOS devices, parasitics & layout-dep.

Layout optimization & area reduction

Cross-functional collaboration

Complex analog blocks handling

Tools

Cadence Virtuoso

Job description

Job Description – Analog Layout Engineer

Position: Analog Layout Engineer

Experience: 4+ Years

Availability: Immediate to 15 Days

Technology: Lower-Node / Advanced Process Technologies

Role Overview

We are looking for experienced Analog Layout Engineers with strong hands-on expertise in custom/analog layout development for lower-node and advanced semiconductor technologies. The candidate will be responsible for developing high-quality layouts for analog and mixed-signal blocks while ensuring design robustness, performance, and compliance with physical verification requirements.

Key Responsibilities

• Develop custom analog and mixed-signal layouts for various semiconductor IPs and blocks.
• Work on lower-node technologies and advanced process nodes, preferably FinFET or similar technologies.
• Translate circuit schematics and design requirements into optimized physical layouts.
• Perform complete layout implementation, optimization, and physical verification.
• Handle DRC, LVS, ERC and other physical verification activities and resolve violations.
• Work closely with Analog Design, Circuit Design, Physical Verification and Technology teams to ensure layout quality.
• Analyze and resolve layout-related design issues and improve layout performance.
• Optimize layouts for area, matching, parasitics and performance.
• Perform post-layout verification and debugging.
• Ensure layouts meet foundry design rules and technology requirements.
• Support design reviews, tape-out activities and project milestones.
• Maintain proper documentation and follow established layout methodologies and quality standards.

Required Skills

• 4+ years of relevant experience in Analog / Custom Layout Design.
• Strong hands-on experience with Analog Layout and Physical Design.
• Experience working on lower-node / advanced semiconductor technologies.
• Strong knowledge of DRC, LVS, ERC and physical verification.
• Good understanding of analog layout concepts and matching techniques.
• Experience with Cadence Virtuoso or equivalent custom layout tools.
• Good understanding of CMOS devices, parasitics and layout-dependent effects.
• Experience in handling complex analog blocks and resolving layout issues.
• Ability to work independently as well as collaboratively with cross-functional teams.

Preferred Experience

Experience with layout of any of the following blocks will be an advantage:

• PLL / DLL
• ADC / DAC
• Bandgap / Reference circuits
• LDO / Power Management
• ComparatorsSerDes / High-speed interfaces
• Mixed-signal IPs
• Memory-related analog circuits

Candidate Profile

We are looking for candidates who have strong hands-on Analog Layout experience, particularly in advanced/lower-node technologies, with good exposure to physical verification and tape-out environments.

Notice Period: Immediate to 15 Days preferred.