Analog Layout Design Engineer

UST; Hyderabad; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

UST in Hyderabad is seeking an experienced Analog Mixed Signal Layout Engineer to work on high-speed blocks for advanced nodes. Immediate to 1-month joiners are preferred. You will design, debug, and validate layouts, ensuring all verification flows and sign-off views are complete.

Required 6–9 years of hands-on layout experience with Cadence tools (Virtuoso EXL/GXL), Calibre, and scripting; ownership mentality and coordination across tasks are essential.

Qualifications

• 6-9 years of hands-on experience in block/module layouts.
• Proficient in Cadence tools for layout design and verification.
• Experience with advanced nodes (TSMC 5nm or lower) is required.

Responsibilities

• Custom layouts for high-speed analog/digital blocks in TSMC 5nm or lower.
• Independent debugging and resolving layout fixes in verification flows
• Flexible to take different tasks in project and own blocks & tasks assigned.
• Execute tasks with minimum supervision and tracking
• Create and check all relevant design views using sign-off tools
• Documentation as per requirement.

Skills

Layout design

Cadence

Scripting

Excel

Education

B.Tech/B.E./MS /M.E. /M tech in Electrical Engineering

Tools

Cadence Virtuoso EXL/GXL

Calibre

Job description

Role & responsibilities

Looking for only IMMEDIATE to 1Month Joiners.

Analog Mixed Signal Layout Engineer:

Responsibilities will include but not limited to following:

• Custom layouts for High-Speed Custom Analog/Digital blocks, such as Ring Oscillators, Dividers, Bias Blocks (Voltage & Current references), pre-drivers etc. in TSMC 2nm & 3nm,
• Independent in debugging and resolving the layout fixes in various verification flows
• Flexible to take different tasks in project.
• Execute tasks with minimum supervision/tracking
• Have accountability and ownership on blocks & tasks assigned.
• Completed layout designs, with desired quality, with all specified verification flows clean
• Create and check all relevant design views using sign-off tools.
• Documentation as per requirement.

Desired Qualification:

• B.Tech/B.E./MS /M.E. /M tech in Electrical Engineering
• 6-9 Years of hands-on experience in block/module layouts with Cadence Layout design tools, exp in TSMC 5nm or lower node is must
• Well versed with layout design and verification tools - Cadence Virtuoso EXL/GXL, Calibre etc.
• Knowledge of scripting (SHELL, PERL, SKILL), excel is good to have.