Analog Layout Engineer | 4+ Years

leadIC Design Pvt Ltd; Bengaluru; Hybrid; INR 3,000,000 - 5,400,000; Full time

Job summary

LeadIC Design Pvt Ltd invites an experienced Analog Layout Engineer to join our team in Bengaluru with hybrid work flexibility. The role focuses on full-custom analog and mixed-signal IC layouts, leveraging Cadence Virtuoso and cutting-edge nodes such as 2nm/3nm/5nm/7nm.

You will collaborate with circuit designers to optimize matching, parasitics, and tape-out readiness. Ideal candidates have 4–8 years of hands-on experience, strong DRC/LVS/PEX discipline, and the ability to contribute to design

Qualifications

• 4–10 years of Analog Layout engineering experience.
• Hands-on experience with TSMC 2nm/3nm/5nm/7nm process nodes.
• Proficient in Cadence Virtuoso and layout verification.

Responsibilities

• Design and implement full-custom analog and mixed-signal IC layouts using Cadence Virtuoso.
• Develop precision layouts for analog circuits, ensuring device matching and symmetry.
• Apply common-centroid, interdigitation and shielding to minimize mismatch and parasitics.
• Perform and debug DRC, LVS, ERC, and PEX to achieve layout sign-off readiness.
• Optimize parasitics while meeting performance, area and reliability goals.
• Collaborate with circuit designers to resolve layout-related issues.
• Support physical verification, design iterations and tape-out activities.
• Follow process design rules and node-specific layout guidelines.

Skills

Analog Layout

Full-custom design

Device matching

Common-centroid layout

Parasitic optimization

Layout debugging

Tape-out support

Tools

Cadence Virtuoso

Job description

Notice Period: Immediate to 30 days only

About the Role

Analog Layout Engineer | 4–10 Years

Company: LeadIC Design Pvt Ltd

Employment Type: Full-time

Workplace Type: Hybrid

Location: Bengaluru,Pune, Hyderabad

Experience: 4–8 years

Notice Period: Immediate to 30 days only

LeadIC Design is looking for experienced Analog Layout Engineers with strong expertise in full-custom analog and mixed-signal IC layout, particularly at advanced technology nodes.

The ideal candidate will have hands‑on experience with TSMC 2nm, 3nm, 5nm, or 7nm technologies and a solid understanding of device matching, parasitic optimization, physical verification, and tape‑out requirements.

Key Responsibilities

• Design and implement full-custom analog and mixed-signal IC layouts using Cadence Virtuoso.
• Develop precision layouts for analog circuits, ensuring device matching, symmetry, and optimal floorplanning.
• Apply common-centroid, interdigitation, shielding, and other layout techniques to minimize mismatch and parasitic effects.
• Perform and debug DRC, LVS, ERC, and PEX checks to achieve layout sign‑off readiness.
• Optimize parasitic resistance and capacitance while meeting performance, area, and reliability requirements.
• Collaborate with circuit designers and verification teams to resolve layout-related issues.
• Support physical verification, design iterations, and tape‑out activities.
• Follow process design rules and technology‑specific layout guidelines for advanced semiconductor nodes.

Required Qualifications

• Experience: 4–10 years of relevant Analog Layout Engineering experience.
• Technology: Hands‑on experience with TSMC 2nm / 3nm / 5nm / 7nm process nodes.
• EDA Tool: Strong proficiency in Cadence Virtuoso.
• Layout Expertise: Full‑custom analog and mixed‑signal IC layout.
• Physical Verification: Practical experience with DRC, LVS, ERC, and PEX.
• Core Skills: Device matching, common‑centroid layout, shielding, parasitic optimization, and layout debugging.
• Tape‑out: Experience supporting layout sign‑off and tape‑out activities.
• Availability: Must be available to join immediately or within 30 days.

Preferred Skills

• Experience working with advanced‑node analog or mixed‑signal designs.
• Understanding of layout‑dependent effects, parasitic extraction, and matching‑sensitive circuits.
• Experience collaborating with analog design and physical verification teams.