Analog Layout

Tech Mahindra; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Tech Mahindra Silicon Engineering in Bengaluru leads advanced silicon design across IP, Sub‑System and SoC levels, delivering end‑to‑end solutions for global clients from RTL to post‑silicon support.

The Analog Layout Engineer role focuses on full‑custom analog and mixed‑signal layouts for cutting‑edge processes (2nm–5nm), collaborating with Analog Design, Verification and Reliability teams to meet power, performance, area, yield and manufacturability targets, including tapeout readiness and

Qualifications

• BE/BTech/ME/MTech in Electronics or related field is required.
• Strong experience in analog and mixed‑signal layouts with physical design focus.
• Experience with FinFET/GAA technologies and advanced nodes.
• Proficiency in layout verification and reliability checks.

Responsibilities

• Design full‑custom analog and mixed‑signal layouts for IP blocks.
• Perform layout implementation, DRC/LVS checks and parasitic extraction.
• Collaborate with analog design and reliability teams for tapeout readiness.
• Develop automation scripts to improve layout productivity.

Skills

Analog Layout

Custom Layout Design

Mixed-Signal Layout

RF/High-Speed Layout

Layout Verification

EM/IR awareness

Problem solving

Education

BE/BTech/ME/MTech in Electronics or related

Tools

EDA tools

Job description

Brief About Tech Mahindra – Silicon Engineering

Tech Mahindra Silicon Engineering is a key part of Tech Mahindra’s semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, networking, and industrial clients. The practice focuses on VLSI, Embedded Systems, SoC Design, and Platform Engineering, supporting customers from architecture and RTL design through implementation, verification, validation, and post-silicon support.

The Silicon Engineering unit works across IP, Sub-System, and SoC-level development, offering deep expertise in areas such as Physical Design, RTL Design, Design Verification, DFT, Analog/Mixed-Signal Design, Custom Layout, Post-Silicon Validation, Embedded Software, and System Engineering. Teams leverage industry-leading EDA tools and advanced implementation methodologies to deliver high-performance, low-power, and manufacturable silicon solutions.

Backed by Tech Mahindra’s global engineering DNA, the Silicon Engineering practice collaborates with leading semiconductor and technology companies worldwide, serving as an extended engineering arm to accelerate silicon development programs, optimize design quality, and enable faster time-to-market for next-generation SoCs and products.

About the Role – Analog Layout Engineer

In this exciting role, you will be responsible for full-custom Analog and Mixed-Signal Layout Design for advanced semiconductor products across cutting-edge process technologies. The ideal candidate will have hands‑on experience in TSMC 2nm, 3nm, and 5nm nodes. Additionally, candidates with strong expertise in Samsung advanced nodes (3nm, 4nm, and below) will also be considered.

You will work closely with Analog Design, Physical Verification, Reliability, Process Technology, and Foundry teams to develop highly optimized custom layouts that meet stringent Power, Performance, Area (PPA), Reliability, Yield, and Manufacturability requirements.

The role involves layout implementation, physical verification, parasitic extraction, matching verification, reliability checks, and tapeout support using industry‑standard EDA tools and methodologies.

Responsibilities – Key Responsibilities

• Develop full‑custom analog and mixed‑signal layouts for IPs such as PLLs, ADCs, DACs, LDOs, Bandgap References, Charge Pumps, High‑Speed Interfaces, SerDes, and Analog Front‑End blocks.
• Execute layout design and implementation in TSMC 5nm, 3nm, and 2nm technologies or Samsung 4nm, 3nm, and advanced process nodes.
• Ensure compliance with foundry design rules and reliability requirements.
• Perform physical verification including: DRC, LVS, ERC, PEX and Antenna Checks
• Analyze parasitic extraction results and support post‑layout simulations.
• Optimize layouts for area, matching accuracy, performance, manufacturability, and yield.
• Work closely with circuit designers to resolve layout‑related performance and functionality issues.
• Collaborate with reliability teams for EM/IR, ESD, Latch‑up, and aging‑related considerations.
• Drive physical verification closure and tapeout readiness.
• Develop automation scripts to improve layout productivity and verification efficiency.
• Participate in design reviews, customer discussions, methodology improvements, and tapeout activities.
• Collaborate with global engineering teams to meet project milestones, quality standards, and silicon schedules.

Qualifications

BE/BTech/ME/MTech degree in Electronics, Electrical Engineering, Microelectronics, VLSI Design, Semiconductor Engineering, or related disciplines.

Required Skills

• Strong experience in Analog Layout and Custom Layout Design.
• Advanced FinFET/GAA technologies
• Expertise in Analog and Mixed‑Signal blocks including PLL, ADC, DAC, Bandgap, LDO, Charge Pump, SerDes, and IO layouts.
• Knowledge of EM/IR, ESD, Latch‑up, and reliability verification methodologies.
• Familiarity with semiconductor manufacturing processes and advanced technology nodes.
• Strong debugging, analytical, problem‑solving, communication, and stakeholder management skills.
• Ability to work effectively in global cross‑functional semiconductor engineering teams.

Preferred Experience

• 4 to 12 years of experience in Analog Layout, Custom Layout, or Mixed‑Signal Layout Design.
• Experience working on advanced‑node products for: AI/ML Accelerators, HPC Processors, Networking SoCs, Mobile Platforms, Automotive Semiconductors,Data Center Silicon
• Exposure to technology migration across multiple foundries.
• Experience supporting advanced‑node tapeouts and silicon bring‑up activities.