AMS Layout Engineer

Cyient; Hyderabad; On-site; INR 900,000 - 1,800,000; Full time

Job summary

Cyient in Hyderabad/Bangalore is seeking an experienced AMS Layout Engineer to translate schematics into transistor- and block-level analog/mixed-signal layouts using SMOS10HV processes, with focus on DRC/LVS, parasitic extraction, and post-layout support.

You will work closely with circuit designers to ensure hierarchy fidelity, perform layout signoff, support tape-out activities, and drive documentation across the layout flow.

Qualifications

• Bachelor's or Master's degree in Electronics, VLSI, Microelectronics or related field.
• Hands-on experience in SMOS10HV process technology.
• Strong experience in Analog Mixed-Signal (AMS) Layout Design.
• Good understanding of analog layout methodologies and device matching techniques.

Responsibilities

• Develop transistor-level and block-level AMS layouts in SMOS10HV technology.
• Create and optimize floorplans considering performance, matching, area, routing, and reliability.
• Translate sub-block schematics into physical layouts while maintaining simulation hierarchy.
• Implement layouts per design docs, guidelines, feedback, and back-annotation needs.
• Ensure one-to-one correspondence between layout and schematic devices.
• Perform DRC and resolve violations to achieve clean signoff.
• Perform LVS verification and resolve discrepancies to closure.
• Comply with foundry-specific layout rules and process requirements.
• Generate extracted netlists for post-layout simulation and back-annotation.
• Participate in layout reviews and document observations and recommendations.

Skills

AMS Layout

Analog layout

Device matching techniques

Symmetry requirements

Common-centroid layouts

Interdigitated structures

Guard rings and shielding

Floorplanning

Hierarchy-based layout

Education

Bachelor's or Master's degree in Electronics Engineering, VLSI, Microelectronics, or related field

Tools

Cadence Virtuoso

Mentor Calibre (DRC/LVS/PEX)

Cadence Pegasus

Synopsys IC Validator

Custom Compiler

Job description

Job Description - AMS Layout Engineer

Job Title

AMS Layout Engineer

Experience

3-8 Years (can be adjusted based on hiring needs)

Location

Bangalore/Hyderabad

Job Summary

We are seeking a skilled AMS (Analog Mixed-Signal) Layout Engineer with hands‑on experience in BCD technolgies with nodes in the range of 40nm to 180nm. The candidate will be responsible for implementing high-quality analog and mixed-signal layouts from schematics, ensuring compliance with design specifications, foundry rules, and signoff requirements. The ideal candidate should possess strong expertise in floorplanning, layout execution, DRC/LVS closure, parasitic extraction, and post-layout support while collaborating closely with circuit design engineers throughout the development cycle.

Key Responsibilities

• Develop transistor-level and block-level Analog Mixed-Signal (AMS) layouts in SMOS10HV technology.
• Create and optimize floorplans considering performance, matching, area, routing, and reliability requirements.
• Translate sub-block schematics into physical layouts while maintaining the same hierarchy used in simulations.
• Implement layouts according to design documentation, layout guidelines, customer feedback, review comments, and back‑annotation requirements.
• Ensure one-to-one correspondence between layout implementation and parameterized devices used in schematic simulations.
• Perform Design Rule Check (DRC) and resolve violations until achieving a clean signoff database.
• Perform Layout Versus Schematic (LVS) verification and resolve discrepancies until successful closure.
• Ensure compliance with all foundry‑specific layout rules and process requirements.
• Generate extracted netlists and provide them to Design Engineers for post‑layout simulation and back‑annotation activities.
• Participate in layout reviews and implement corrective actions based on review findings.
• Maintain and update block review documentation with layout implementation details, observations, and recommendations.
• Work closely with circuit designers to optimize layout quality, performance, and manufacturability.
• Support tape‑out activities and ensure timely delivery of layout milestones.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, VLSI, Microelectronics, or a related field.
• Hands‑on experience in SMOS10HV process technology.
• Strong experience in Analog Mixed‑Signal (AMS) Layout Design.
• Good understanding of:
  • Analog layout methodologies
  • Device matching techniques
  • Symmetry requirements
  • Common-centroid layouts
  • Interdigitated structures
  • Guard rings and shielding
• Experience performing:
  • oDRC
  • oLVS
  • oParasitic Extraction (PEX)
  • oLayout signoff activities
• Ability to interpret schematics and convert them into optimized physical layouts.
• Strong understanding of hierarchy‑based layout implementation.

Preferred Skills

• Experience in:
  • oHigh‑voltage analog layouts
  • oPower Management ICs (PMIC)
  • oAutomotive semiconductor products
  • oMixed‑signal IP development
• Knowledge of ESD and latch‑up protection concepts.
• Understanding of post‑layout simulation methodologies.
• Familiarity with reliability and manufacturability requirements.

EDA Tools

• Experience with one or more of the following:
• Cadence Virtuoso
• Mentor Calibre (DRC/LVS/PEX)
• Cadence Pegasus
• Synopsys IC Validator
• Custom Compiler

Key Competencies

• Strong debugging and problem‑solving skills.
• Attention to detail and layout quality.
• Effective communication and collaboration with design teams.
• Ability to work independently and manage complete layout ownership.
• Strong documentation and review skills.

Keywords AMS Layout, Analog Layout, Mixed‑signal Layout, SMOS10HV, High Voltage Layout, Floorplanning, DRC, LVS, PEX, Layout Signoff, Cadence Virtuoso, Calibre, PMIC, Automotive Semiconductor.

Roles and Responsibilities

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.