Analog Layout Engineer

Cyient; Hyderabad; On-site; INR 2,500,000 - 3,800,000; Full time

Job summary

Cyient is seeking a Senior Analog Layout Engineer with strong experience in 7nm FinFET high-speed analog/mixed-signal layout. You will translate schematics to physical layouts, ensure DRC/LVS compliance, and support post-layout verification for robust IPs.

Collaboration with circuit designers and verification teams is essential for successful signoff. The role requires expertise in advanced node layout challenges and post-layout extraction, with opportunities to contribute to high-performance

Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.
• Strong experience in 7nm FinFET technology node layout development.
• Proven expertise in high-speed analog and mixed-signal layout design.
• Hands-on experience with multi-patterning, device matching, parasitic optimization, reliability rules.
• Strong understanding of DRC, LVS, Parasitic extraction (PEX), ERC checks.
• Experience generating extracted netlists and supporting post-layout simulations.
• Excellent analog layout techniques: common centroid, interdigitation, symmetry, matching, shielding, guard rings.
• Ability to read and interpret circuit schematics and design specifications.

Responsibilities

• Create and optimize floorplans for analog and mixed-signal blocks in 7nm FinFET technology.
• Translate sub-block schematics into physical layouts while maintaining hierarchy and design intent.
• Perform detailed transistor-level and block-level layout for high-speed circuits.
• Ensure layout matches parameterized devices and schematic hierarchy for signoff.
• Follow design documentation and feedback during layout execution.
• Resolve DRC violations until layout is clean.
• Resolve LVS discrepancies until signoff.
• Ensure compliance with foundry rules and reliability requirements.
• Generate extracted netlists for post-layout simulations.
• Collaborate with Design Engineers for post-layout verification.
• Document layout methodologies and notes in block reviews.
• Participate in design reviews and implement corrective actions.
• Optimize layout for area, matching, parasitics, signal integrity, EM, manufacturability.

Skills

7nm FinFET layout

High-speed analog layout

DRC/LVS/PEX knowledge

Schematic-to-layout interpretation

Analog layout techniques: centroid

Scripting: Python/Perl/Tcl

Education

Bachelor's or Master's in Electronics / Electrical / Microelectronics

Tools

Cadence Virtuoso

Calibre

PEX tools

Job description

Job Description – Senior Analog Layout Engineer (7nm FinFET or below High-Speed Design)

Position Title

Senior Analog Layout Engineer – 7nm FinFET High-Speed Layout

Experience

5–12 Years (depending on complexity and ownership level)

Location

Kolkata / Hyderabad / Bangalore

Role Summary

We are seeking a highly skilled Senior Analog Layout Engineer with strong experience in advanced FinFET technology nodes (7nm and below) and high-speed analog/mixed-signal layout design. The ideal candidate will be responsible for translating schematics into high-quality physical layouts while ensuring compliance with foundry design rules, performance requirements, and project specifications. The engineer will work closely with circuit designers and verification teams to develop robust layouts for high-speed analog and mixed-signal IPs, ensuring successful DRC/LVS closure and post-layout verification.

Key Responsibilities

• Create and optimize floorplans for analog and mixed-signal blocks in advanced 7nm FinFET technology.
• Translate sub-block schematics into physical layouts while maintaining hierarchy and design intent.
• Perform detailed transistor-level and block-level layout implementation for high-speed circuits.
• Ensure layout matches parameterized devices (PCells) and simulation hierarchy on a one-to-one basis.
• Follow design documentation, review comments, customer feedback, and back-annotation requirements during layout execution.
• Perform and resolve Design Rule Check (DRC) violations until the layout is fully clean.
• Perform and resolve Layout Versus Schematic (LVS) discrepancies until successful signoff.
• Ensure layouts comply with all foundry‑specific design rules and reliability requirements.
• Generate extracted netlists for post‑layout simulations and back‑annotation activities.
• Work closely with Design Engineers (DEs) to support post‑layout verification and performance closure.
• Document layout methodologies, notes, and implementation details in block review documents.
• Participate in design reviews and implement corrective actions resulting from layout reviews.
• Optimize layout for area, matching, parasitics, signal integrity, electromigration (EM), and manufacturability.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.
• Strong experience in 7nm FinFET technology node layout development.
• Proven expertise in high‑speed analog and mixed‑signal layout design.
• Hands‑on experience with advanced node layout challenges including:
  • Multi‑patterning awareness
  • Device matching
  • Parasitic optimization
  • Reliability rules
• Strong understanding of:
  • DRC
  • LVS
  • Parasitic extraction (PEX)
  • ERC checks
• Experience generating extracted netlists and supporting post‑layout simulations.
• Excellent understanding of analog layout techniques:
  • Common centroid
  • Interdigitation
  • Symmetry
  • Matching
  • Shielding
  • Guard rings
• Ability to read and interpret circuit schematics and design specifications.

Preferred Skills

• Experience with advanced nodes such as 3nm, 4nm, 5nm, 6nm, 7nm, 10nm, or 12nm FinFET.
• Experience in layouts for:
  • PLLs
  • High‑speed SerDes
  • Clocking circuits
  • Data converters (ADC/DAC)
  • High Bandwidth Memory
  • RF or mixed‑signal IPs
• Knowledge of EMIR analysis and reliability verification.
• Familiarity with process variation and layout‑dependent effects (LDE).
• Experience working with global semiconductor customers.
• Knowledge of automation or scripting (SKILL, Perl, Python, Tcl).
• Experience in IP development for high‑performance computing, networking, or AI applications.

cyient.com

Keywords: Analog Layout, Mixed‑Signal Layout, FinFET, 7nm, High‑Speed Layout, DRC, LVS, PEX, Floorplanning, Cadence Virtuoso, Calibre, SerDes, PLL, HBM.

Roles and Responsibilities

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.