Senior DFT Engineer

Cadence; Hyderabad; On-site; INR 1,000,000 - 2,000,000; Full time

Job summary

Cadence is seeking experienced DFT engineers in Hyderabad with 3-12 years of expertise. Responsibilities include collaboration across teams, creating test structures for DFT, and engaging in post-silicon bring-up. Candidates must have proficiency in SCAN/ATPG/JTAG/MBIST, chip tape out experience, and strong teamwork skills. This role offers an opportunity to be part of an inclusive team committed to diversity.

Qualifications

• 3-12 years of expertise in DFT engineering.

Responsibilities

• Collaborate with teams to resolve DFT issues.
• Create test structures for DFT and IP integration.
• Engage in post-silicon bring-up and debugging.

Skills

Strong proficiency in SCAN/ATPG/JTAG/MBIST

Hands-on experience in chip tape out

Expertise in gate-level simulation

Proficiency in creating test structures for DFT

Skill in scan insertion techniques

Experience in Memory BIST generation

Understanding of Analog PHY and Macro tests

Familiarity with JTAG standards

Knowledge of test mode timing constraints

Ability to collaborate across teams

Proficiency in Cadence/Tessent tools

Experience in post-silicon bring up

Proficiency in Perl/Tcl scripting

Strong teamwork and communication skills

Tools

Cadence/Tessent

Job description

About the Role

Cadence Hyderabad and PUNE is currently seeking experienced DFT engineers with 3-12 years of expertise for their team.

Responsibilities

• Strong proficiency in SCAN/ATPG/JTAG/MBIST
• Hands‑on experience in chip tape out, including chip ATE bring up
• Expertise in gate‑level simulation, encompassing both timing (SDF) and no‑timing simulations (ATPG/MBIST/JTAG)
• Proficiency in creating test structures for DFT, IP integration, ATPG fault models, test point insertion, and coverage enhancement techniques
• Skill in scan insertion techniques at both block and chip top levels
• Experience in Memory BIST generation, insertion, and verification at RTL/Netlist levels
• Understanding of Analog PHY and Analog Macro tests
• Familiarity with JTAG standards such as IEEE 1149.1/IEEE1149.6
• Knowledge of test mode timing constraints and block/chip STA flows
• Ability to collaborate across teams to resolve DFT issues with design, synthesis, physical design, and STA teams
• Proficiency in industry‑standard tools like Cadence/Tessent for scan insertion, ATPG, MBIST, and JTAG
• Experience in post‑silicon bring up and debug on ATE
• Proficiency in Perl/Tcl scripting
• Strong teamwork and communication skills to engage effectively with diverse global teams
• Demonstrated sense of responsibility and ownership for successful tape out and post‑silicon bring up projects

Qualifications

3-12 years of expertise in DFT engineering.

Required Skills

• Strong proficiency in SCAN/ATPG/JTAG/MBIST
• Hands‑on experience in chip tape out, including chip ATE bring up
• Expertise in gate‑level simulation, encompassing both timing (SDF) and no‑timing simulations (ATPG/MBIST/JTAG)
• Proficiency in creating test structures for DFT, IP integration, ATPG fault models, test point insertion, and coverage enhancement techniques
• Skill in scan insertion techniques at both block and chip top levels
• Experience in Memory BIST generation, insertion, and verification at RTL/Netlist levels
• Understanding of Analog PHY and Analog Macro tests
• Familiarity with JTAG standards such as IEEE 1149.1/IEEE1149.6
• Knowledge of test mode timing constraints and block/chip STA flows
• Ability to collaborate across teams to resolve DFT issues with design, synthesis, physical design, and STA teams
• Proficiency in industry‑standard tools like Cadence/Tessent for scan insertion, ATPG, MBIST, and JTAG
• Experience in post‑silicon bring up and debug on ATE
• Proficiency in Perl/Tcl scripting
• Strong teamwork and communication skills to engage effectively with diverse global teams
• Demonstrated sense of responsibility and ownership for successful tape out and post‑silicon bring up projects

Preferred Skills

None specified.

Pay range and compensation package

Not specified.

Equal Opportunity Statement

Cadence is committed to diversity and inclusivity.