DFT-MBIST Engineer

Proxelera; Bengaluru Urban; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

A semiconductor company in Bangalore Urban, Karnataka, is seeking a Manager - Talent Acquisition to lead the DFT strategy in a complex SoC environment. The role involves hands-on experience with DFT tools, solving challenging testability problems, and working alongside design and test teams. A strong background in DFT architecture and scripting is essential for success in this position.

Qualifications

• Experience leading DFT strategy in semiconductor design.
• Strong understanding of DFT tools and methodologies.
• Ability to work cross-functionally with design and test teams.

Responsibilities

• Lead DFT architecture, planning, and execution for SoCs.
• Build and integrate scan and compression flows.
• Own ATPG generation and drive yield improvements.
• Use scripting to optimize DFT flows.

Skills

DFT architecture

Testability problem-solving

Scripting (TCL/Python/Perl)

Coverage analysis

RTL coding (Verilog/SystemVerilog)

Hands-on experience with Tessent

Tools

Tessent

DFTAdvisor

SpyGlass-DFT

ATPG tools

Job description

Manager - Talent Acquisition (Talent Sourcing Expert | Recruitment Enthusiast | Semiconductor Industry | Connecting Talent with Opportunities)

We’re looking for someone who can walk into a complex SoC environment, take charge of the entire DFT strategy, and push it all the way through silicon. If you enjoy solving hard testability problems, obsess over coverage numbers, and like working across design, PD, and test teams, this role will suit you well.

Responsibilities

• Lead DFT architecture, planning, and execution for mid to large-scale SoCs.
• Build and integrate scan, MBIST/LBIST, boundary scan (IEEE 1149.1/1500), and compression flows.
• Own ATPG generation, coverage analysis, and drive yield and defect-escape improvements.
• Work hands‑on with Tessent, DFTAdvisor, SpyGlass-DFT, ATPG, and fault simulation tools.
• Perform RTL and gate-level DFT insertion with an eye on timing, area, and power trade‑offs.
• Support silicon bring‑up, ATE vector debug, and post‑silicon diagnostics/failure analysis.
• Write clean RTL (Verilog/SystemVerilog) and maintain solid fundamentals in STA.
• Use scripting (TCL/Python/Perl) to automate, optimize, and strengthen DFT flows.
• Partner with design, PD, and ATE teams and produce clear, reliable documentation.

Job Details

• Seniority level: Mid‑Senior level
• Employment type: Full‑time
• Job function: Design
• Industry: Semiconductor Manufacturing
• Location: Bangalore Urban, Karnataka, India