08303 DFT Engineer (Senior/Manager)

Cephas Consultancy Services Private Limited; Bengaluru; On-site; INR 600,000 - 1,200,000; Full time

Job summary

Cephas Consultancy Services Private Limited in Bengaluru is seeking an experienced DFT Engineer to design and implement BSCAN/MBIST based test strategies for SoCs. The role focuses on scan, ATPG, and fault-model driven debugging in a fast-paced environment.

You will collaborate with cross-functional teams and customer engineers, leveraging Cadence, Tessent and Synopsys tools for timing, synthesis and post-silicon bring-up activities.

Qualifications

• Experience in BSCAN, MBIST, SCAN, ATPG and related concepts.
• Experience with at least one: MBIST insertion, Scan insertion, ATPG pattern generation and simulations.
• Exposure to Cadence/Siemens Tessent/Synopsys tools.
• Familiarity with fault models such as stuck-at, TDF, IDDQ and scan test coverage techniques.
• Strong debugging and cross-functional communication skills.

Responsibilities

• Design and implement SoC level DFT, OCC/OPCG insertion, EDT/Compression logic insertion.
• Handle clock module for scan, post-silicon bring-up and production support.
• Provide test mode timing constraints to STA and PD teams.
• Mentor DFT engineers and coordinate with customer teams.
• Utilize GUI-based simulators for debugging and verification.

Skills

BSCAN

MBIST

ATPG

Simulation

Debugging

Cross-functional communication

Tools

Cadence

Siemens Tessent

Synopsys

VCS

NCSim

Xcelium

Job description

About this position

Positions:20 Full Time
Experience
3 - 15 Years

Experience: 3-15 Years

Role -

• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
• Should have experience in atleast one : MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
• Good to have worked on zero delay as well as SDF Timing Simulations.
• Should have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
• Good to have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
• Candidate should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
• The candidate should have experience of providing test mode timing constraints to STA and PD teams.

Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.

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