Senior Staff DFT Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,800,000 - 2,600,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd is seeking a Senior Staff DFT Engineer to own DFT architecture and drive ATPG, MBIST and test compression for complex SoC designs. You will collaborate across RTL, Physical Design and Silicon teams through tapeout and bring-up, while developing DFT flows and automation using Tcl, Python and Perl.

The ideal candidate has hands-on leadership in DFT architecture, signoff and silicon bring-up, with deep expertise in DFT timing, coverage and test power for advanced-node

Qualifications

• Hands-on experience with DFT architecture and signoff in complex SoCs.
• Proven ability to drive DFT flows end-to-end across tapeout.
• Experience with ATPG, MBIST, JTAG, and test compression.
• Strong scripting and cross-functional leadership.
• Deep understanding of timing, power, and coverage in DFT contexts.

Responsibilities

• Own DFT architecture and methodology for complex SoC/full-chip designs.
• Drive Scan insertion, ATPG, MBIST, JTAG and test compression implementation.
• Develop and validate DFT specifications, test modes and coverage targets.
• Drive ATPG pattern generation, coverage analysis and fault debug.
• Analyze and resolve DFT timing, test power, coverage and physical implementation issues.
• Collaborate with RTL, Physical Design, STA, Verification and Silicon teams through tapeout and bring-up.
• Develop DFT flows and automation using Tcl/Python/Perl.

Skills

DFT architecture

ATPG

Scan

MBIST

JTAG

Test compression

Scripting Tcl/Python/Perl

Tools

Synopsys DFTMAX

TetraMAX

Siemens Tessent

Job description

We are looking for a Senior Staff DFT Engineer with deep hands-on expertise in DFT architecture, implementation, ATPG and silicon bring-up for complex SoC designs.

Key Responsibilities

• Own DFT architecture and methodology for complex SoC/full-chip designs.
• Drive Scan insertion, ATPG, MBIST, JTAG and test compression implementation.
• Develop and validate DFT specifications, test modes and coverage targets.
• Drive ATPG pattern generation, coverage analysis and fault debug.
• Analyze and resolve DFT timing, test power, coverage and physical implementation issues.
• Collaborate with RTL, Physical Design, STA, Verification and Silicon teams through tapeout and bring-up.
• Develop DFT flows and automation using Tcl/Python/Perl.

Core Technical Skills

• Strong expertise in Scan, ATPG, MBIST, JTAG, EDT/Test Compression.
• Hands-on experience with Synopsys DFTMAX/TestMAX, TetraMAX or Siemens Tessent.
• Deep understanding of stuck-at, transition, path-delay and memory fault models.
• Strong knowledge of DFT architecture, testability, coverage and test modes.
• Experience with advanced-node SoCs and full-chip DFT signoff.
• Strong scripting, debugging and cross-functional technical leadership.

Ideal Candidate:

A deeply hands-on DFT technical leader capable of owning SoC DFT from architecture through implementation, signoff and silicon bring-up.