Sr. DFT Engineer

NXP Semiconductors; Maharashtra; On-site; INR 2,500,000 - 5,000,000; Full time

Job summary

NXP Semiconductors in India is seeking a Senior DFT Engineer to design, implement, and verify DFT architectures for complex SoCs. You will collaborate with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.

Key responsibilities include implementing scan, MBIST, LBIST, and boundary scan, developing ATPG patterns, and coordinating with ATE teams for silicon bring-up. Strong knowledge of DFT methods and fault models is required.

Qualifications

• Design and implement DFT architectures for complex SoCs.
• Develop and verify scan, MBIST, LBIST and boundary scan.
• Collaborate with RTL and physical design for DFT insertion and timing.
• Verify DFT at RTL and gate level simulations and ATE bring-up readiness.

Responsibilities

• Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan).
• Develop and integrate scan insertion, test compression, and ATPG patterns.
• Implement memory BIST and logic BIST strategies.
• Collaborate with RTL and physical design teams for DFT insertion and timing closure.
• Perform DFT verification at RTL and gate-level simulations.
• Work with ATE teams for test program development and silicon bring-up.
• Optimize test coverage, pattern count, and test time.

Skills

DFT methodologies

ATPG tools

UPF/CPF low-power DFT

Fault models

Physical design constraints

Silicon bring-up

JTAG

Education

Bachelor’s or Master’s in Electrical/Electronics Engineering

Tools

JTAG

Job description

Senior DFT Engineer: You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs. You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.

Key Responsibilities

• Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan).
• Develop and integrate scan insertion, test compression, and ATPG patterns.
• Implement memory BIST and logic BIST strategies.
• Collaborate with RTL and physical design teams for DFT insertion and timing closure.
• Perform DFT verification at RTL and gate-level simulations.
• Work with ATE teams for test program development and silicon bring-up.
• Optimize test coverage, pattern count, and test time.

Required Skills

• Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG.
• Hands‑on experience with industry standard ATPG tools.
• Proficiency in UPF/CPF‑based low‑power DFT.
• Knowledge of fault models (stuck‑at, transition, path delay).
• Familiarity with physical design constraints for DFT.
• Experience in silicon debug and ATE bring‑up.

Preferred Qualifications

• Pas experience with SoC level DFT
• Exposure to high‑speed interfaces and DFT for mixed‑signal blocks.
• Strong problem‑solving and communication skills.

Education

• Bachelor’s or Master’s in Electrical/Electronics Engineering.