DFT (Design for Testability) Lead

7Rays Semiconductors; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

7Rays Semiconductors in Bengaluru seeks a hands-on DFT engineer with strong knowledge of BSCAN, MBIST, SCAN, ATPG concepts. You will be hands-on with MBIST insertion, scan insertion, ATPG pattern generation, and simulations using Cadence/Siemens/Synopsys tools.

You should have worked on zero delay and SDF timing simulations, with strong debugging skills in GUI simulators. The role involves improving scan test coverage, performing test mode timing constraints for STA and PD teams, and

Qualifications

• Clear understanding of BSCAN, MBIST, SCAN, ATPG concepts.
• Hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations.
• Experience with MBIST and BSCAN simulations using Cadence/Siemens/Synopsys tools.
• Experience in zero delay and SDF timing simulations.
• Good debugging skills with GUI simulators (VCS/NCSim/Xcelium).
• Familiarity with fault models like stuck-at, TDF, IDDQ; scan test coverage improvement.

Responsibilities

• Develop and optimize DFT for SoC level with OCC/OPCG insertion and EDT/Compression logic.
• Coordinate with tester/debug teams during post-silicon bring-up and production activities.
• Provide test mode timing constraints to STA and PD teams.
• Mentor DFT engineers and collaborate with cross-functional teams and customer teams.

Skills

DFT concepts

MBIST insertion

Scan insertion

ATPG pattern generation

Simulation debugging

SoC DFT familiarity

cross-functional collaboration

Tools

Cadence Tessent

Siemens Tessent

Synopsys Xcelium/VCS

Job description

At 7Rays Semiconductors (https://7rayssemi.com/), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Role -

• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
• Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
• He/she must have worked on zero delay as well as SDF Timing Simulations.
• Must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
• The candidate should have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
• He/she should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock module handling for scan purposes and post-silicon bring-up and /or production activities with exposure to Tester debug usings shmoo plots and graphs.
• The candidate should have experience of providing test mode timing constraints to STA and PD teams.
• Additional knowledge of perl/tcl scripting will be an advantage.
• Good communication skills and debugging skills are a must to have qualities for this role as it involves cross-functional teams and customer teams communications along with internal DFT team leading and mentoring of DFT Engineers.