Lead ASIC Verification Architect

Synopsys, Inc.; Dublin; Hybrid; EUR 150,000 - 190,000; Full time

Job summary

Synopsys, Inc. seeks a senior verification architect with 12+ years in ASIC verification to lead UVM-based validation of interface IP. You will design advanced testbenches, write constrained random stimulus, and implement assertions to ensure robust silicon.

You will mentor engineers, promote reusable verification IP, and drive coverage closure across multiple projects while advancing formal validation and high-performance debugging techniques.

Qualifications

• Bachelor's or master's degree in computer engineering, Electrical Engineering, or Communications Engineering.
• 12+ years of hands-on ASIC design verification experience with strong focus on UVM-based functional verification.
• Deep expertise in SystemVerilog, including advanced testbench architecture, constrained random verification, and coverage-driven verification.
• Proven experience implementing SystemVerilog Assertions for functional and formal verification flows.
• Strong programming skills in at least two of: C, SystemVerilog, TCL, Perl, or Python.
• Experience with PCI Express and CXL protocols is a strong plus.
• Experience in interface IP verification, formal verification tools like Jasper or VC Formal, and AI-assisted coding tools like Cursor or GitHub Copilot will set you apart.

Responsibilities

• Collaborate with design teams to define verification requirements and translate specs into test plans that cover functional, edge case, and performance scenarios.
• Architect and implement UVM testbench environments, including agents, scoreboards, and reusable verification components for interface IP designs.
• Write System Verilog test sequences and constrained random stimulus to stress designs and uncover corner cases before silicon.
• Implement System Verilog Assertions for simulation-based functional verification and formal verification flows.
• Build and analyze functional and code coverage metrics, identify gaps, and drive coverage closure.
• Lead and mentor a team of verification engineers, teaching UVM methodology, debugging techniques, and testbench architecture best practices.

Skills

UVM verification

SystemVerilog

ASIC verification

Formal verification

Mentoring

C/Python

Education

Bachelor's or master's degree in computer engineering, Electrical Engineering, or Communications Engineering

Tools

Jasper

VC Formal

Cursor

GitHub Copilot

Job description

Synopsys, Inc. seeks a senior verification architect with 12+ years in ASIC verification to lead UVM-based validation of interface IP. You will design advanced testbenches, write constrained random stimulus, and implement assertions to ensure robust silicon.

You will mentor engineers, promote reusable verification IP, and drive coverage closure across multiple projects while advancing formal validation and high-performance debugging techniques.