AI-Driven ASIC Verification Engineer

Synopsys, Inc.; Dublin; On-site; EUR 90,000 - 140,000; Full time

Job summary

Synopsys, Inc. is seeking an ASIC verification engineer who cares about how verification is done as much as what is verified.

You will bring hands-on UVM, automate repetitive steps, and work within AI-assisted flows to review and maintain testbench code and regression infrastructure. You’ll design and deploy reusable verification components for PCIe and CXL IP used in data centers and AI workloads, develop UVM architectures, and collaborate with infrastructure to ensure efficient access to

Qualifications

• Bachelor's or Master's degree in Computer/Electrical/Communications Eng.
• 5+ years in ASIC verification or UVM; 3+ with a Master.
• Strong SystemVerilog and UVM, including testbench architecture.
• Experience using AI coding agents (Cursor, Claude, Copilot).

Responsibilities

• Design, deploy, maintain reusable verification components for PCIe and CXL IP.
• Develop UVM testbench architecture, agents and sequences.
• Extend AI-assisted flows for verification and automation using AI agents.
• Integrate Synopsys tools into the product workflow.

Skills

UVM

SystemVerilog

AI flows

Python

Shell scripting

Education

Bachelors/Masters in EE/CE

Tools

Cursor

Claude Code

GitHub Copilot

Job description

Synopsys, Inc. is seeking an ASIC verification engineer who cares about how verification is done as much as what is verified.

You will bring hands-on UVM, automate repetitive steps, and work within AI-assisted flows to review and maintain testbench code and regression infrastructure. You’ll design and deploy reusable verification components for PCIe and CXL IP used in data centers and AI workloads, develop UVM architectures, and collaborate with infrastructure to ensure efficient access to