Principal ASIC Verification Architect | UVM & Formal

Synopsys Inc; Dublin; On-site; EUR 120,000 - 180,000; Full time

Job summary

Synopsys Inc in Ireland is seeking a senior verification engineer to architect UVM testbenches for interface IP and to drive robust verification strategies.

You will write SystemVerilog sequences, constrained random stimuli, and assertions to stress designs and reveal corner cases before tape-out. A strong emphasis on mentoring and setting verification standards will be part of your impact.

Qualifications

• 12+ years of hands-on ASIC design verification experience with strong focus on UVM-based Functional verification.
• Deep expertise in System Verilog including advanced testbench architecture, constrained random verification, and coverage-driven verification.
• Proven experience implementing System Verilog Assertions for functional and formal verification flows.

Responsibilities

• Collaborate with design teams to define verification requirements and translate specs into test plans that cover functional, edge case, and performance scenarios.
• Architect and implement UVM testbench environments, including agents, scoreboards, and reusable verification components for interface IP designs.
• Write System Verilog test sequences and constrained random stimulus to stress designs and uncover corner cases before silicon.
• Implement System Verilog Assertions for simulation-based verification and formal verification flows.
• Build and analyze functional and code coverage metrics, identify gaps, and drive coverage closure.
• Lead and mentor a team of verification engineers, teaching UVM methodology, debugging techniques, and testbench architecture best practices.

Skills

UVM expertise

SystemVerilog

Constrained random

Formal verification

Python scripting

Mentoring

Testbench architecture

Education

Bachelor/Master in EE/CE

Job description

Synopsys Inc in Ireland is seeking a senior verification engineer to architect UVM testbenches for interface IP and to drive robust verification strategies.

You will write SystemVerilog sequences, constrained random stimuli, and assertions to stress designs and reveal corner cases before tape-out. A strong emphasis on mentoring and setting verification standards will be part of your impact.