Senior ASIC Verification Engineer — DDR/PCIe IP Lead

Synopsys, Inc.; Dublin; Hybrid; EUR 110,000 - 170,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced ASIC Digital Verification Engineer to design and implement verification environments for Interface IP protocols. You will develop verification IP and testbenches using SystemVerilog and UVM, and collaborate with design teams to fix bugs while driving coverage closure.

You will mentor junior engineers and contribute to high-quality ASIC designs that power a range of semiconductor technologies.

Qualifications

• Extensive ASIC digital verification experience focusing on Interface IP protocols (DDR, PCIe, CXL, Ethernet).
• Proficiency with SystemVerilog and UVM methodologies.
• Experience with simulation tools such as VCS or ModelSim.

Responsibilities

• Design and implement verification environments for Interface IP protocols.
• Create and execute detailed test plans to verify ASIC designs.
• Develop and maintain verification IP and testbenches using SystemVerilog and UVM.
• Collaborate with design and architecture teams to identify and fix bugs.
• Perform functional coverage analysis and drive coverage closure.
• Mentor and guide junior verification engineers.

Skills

SystemVerilog

UVM

DDR

PCIe

CXL

Ethernet

Verification methodologies

Tools

VCS

ModelSim

Job description

Synopsys, Inc. is seeking an experienced ASIC Digital Verification Engineer to design and implement verification environments for Interface IP protocols. You will develop verification IP and testbenches using SystemVerilog and UVM, and collaborate with design teams to fix bugs while driving coverage closure.

You will mentor junior engineers and contribute to high-quality ASIC designs that power a range of semiconductor technologies.