Senior UVM Verification Architect for Interface IP

Synopsys, Inc.; Dublin; On-site; EUR 120,000 - 180,000; Full time

Benefits offered by this job

Health benefits

Financial benefits

Job summary

Synopsys, Inc. is seeking a senior verification engineer to lead the creation of UVM-based testbenches for interface IP used in silicon designs. You will architect verification environments, write constrained-random sequences, and implement SV assertions to enable robust verification.

You will mentor a team, drive coverage, and contribute to both functional and formal verification flows, accelerating tape-out schedules.

Qualifications

• Bachelor's or master's degree in computer, electrical, or communication engineering.
• 8+ years of hands-on ASIC design verification with a focus on UVM-based verification.
• Deep expertise in SystemVerilog, testbench architecture, and coverage-driven verification.
• Experience implementing SystemVerilog Assertions for functional and formal verification.
• Strong programming in at least two of C, SystemVerilog, TCL, Perl, or Python.
• Experience with PCI Express and CXL protocols is a strong plus.
• Experience in interface IP verification and AI-assisted coding tools will set you apart.

Responsibilities

• Collaborate with design teams to define verification requirements and translate specs into tests.
• Architect and implement UVM testbenches with agents, scoreboards, and reusable components.
• Write SystemVerilog test sequences and constrained random stimulus to stress designs.
• Implement SystemVerilog Assertions for simulation and formal verification flows.
• Build and analyze functional and code coverage; drive coverage closure.
• Lead and mentor a team of verification engineers on UVM and testbench architecture.

Skills

UVM

SystemVerilog

Formal verification

Constrained random

Education

Bachelor's or master's in Computer/Electrical/communication engineering

Tools

Jasper

VC Formal

GitHub Copilot

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Job description

Synopsys, Inc. is seeking a senior verification engineer to lead the creation of UVM-based testbenches for interface IP used in silicon designs. You will architect verification environments, write constrained-random sequences, and implement SV assertions to enable robust verification.

You will mentor a team, drive coverage, and contribute to both functional and formal verification flows, accelerating tape-out schedules.